iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	2	-7/+111
*	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27	1	-4/+4
*	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27	1	-0/+15
*	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27	1	-17/+57
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	61	-152/+152
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	50	-191/+191
*	New message for completion of build	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	8	-81/+52
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	19	-218/+150
*	Added tests/various/.gitignore	Clifford Wolf	2014-07-26	1	-0/+1
*	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26	3	-0/+28
*	Added support for here documents	Clifford Wolf	2014-07-26	3	-18/+63
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	5	-39/+39
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	12	-27/+33
*	Merge automatic and manual code changes for new cell connections API	Clifford Wolf	2014-07-26	61	-1201/+1247
\|\
\| *	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	36	-123/+169
\| *	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	61	-1201/+1201
\|/
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26	2	-9/+9
*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26	2	-0/+6
*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26	2	-0/+6
*	Use "wget -N" in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-26	1	-2/+2
*	Added "passed" message to make test targets	Clifford Wolf	2014-07-26	1	-0/+9
*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26	2	-17/+63
*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26	2	-0/+71
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	62	-1213/+1234
*	Cosmetic fixes for "make abc"	Clifford Wolf	2014-07-26	1	-2/+3
*	Added "Checklist for adding internal cell types"	Clifford Wolf	2014-07-26	1	-2/+26
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	4	-20/+17
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	35	-582/+259
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	4	-47/+55
*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25	2	-0/+20
*	Added "make vgtest"	Clifford Wolf	2014-07-25	1	-0/+5
*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25	1	-1/+6
*	Renamed some of the test cases in tests/simple to avoid name collisions	Clifford Wolf	2014-07-25	15	-30/+30
*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25	1	-5/+7
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25	3	-4/+8
*	Added more stuff to checklist	Clifford Wolf	2014-07-25	1	-0/+4
*	Updated verific build/test instructions	Clifford Wolf	2014-07-25	2	-13/+11
*	Improvements in "cover" command	Clifford Wolf	2014-07-25	1	-11/+37
*	Removed Minisat dependency on zlib	Clifford Wolf	2014-07-25	5	-13/+43
*	Added more stuff to the checklist	Clifford Wolf	2014-07-25	1	-1/+13
*	Fixed typo in cover id	Clifford Wolf	2014-07-25	1	-1/+1
*	Added "make clean-abc"	Clifford Wolf	2014-07-25	1	-0/+4
*	Further improved "make" prettiness	Clifford Wolf	2014-07-25	1	-5/+10
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	17	-104/+101
*	Updated ABC to hg id "b1e63d18768d"	Clifford Wolf	2014-07-24	1	-1/+1
*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24	1	-9/+45
*	Added cover_list() API	Clifford Wolf	2014-07-24	2	-2/+46
*	Added "make SMALL=1"	Clifford Wolf	2014-07-24	2	-1/+30