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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 03:17:35 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 03:41:53 +0200 |
| commit | 7f1789ad1bb978132e8e09fee54ded81b370fcb3 (patch) | |
| tree | 9d83b8a9f3ccd70418086bd17ec237e9dc1f5775 | |
| parent | cd699254377b08729342026056f97d9d6bc1e2f3 (diff) | |
| download | yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.tar.gz yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.tar.bz2 yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.zip | |
Fixed typo in cover id
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f741e2a34..6bb395ec2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1866,7 +1866,7 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { - cover("kernel.rtlil.sigspec.extend_0"); + cover("kernel.rtlil.sigspec.extend_u0"); pack(); |