diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 22:47:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 23:10:58 +0200 |
commit | 6aa792c864444324a1b140c2b63bd860f0cc3914 (patch) | |
tree | 07b2bf3003864337df616a21374c046ddc352c62 | |
parent | 7a608437c65e9646ed229055d61b310e7d93e37e (diff) | |
download | yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.gz yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.bz2 yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.zip |
Replaced more old SigChunk programming patterns
-rw-r--r-- | backends/autotest/autotest.cc | 5 | ||||
-rw-r--r-- | backends/blif/blif.cc | 14 | ||||
-rw-r--r-- | backends/edif/edif.cc | 15 | ||||
-rw-r--r-- | backends/ilang/ilang_backend.cc | 2 | ||||
-rw-r--r-- | backends/intersynth/intersynth.cc | 16 | ||||
-rw-r--r-- | backends/spice/spice.cc | 16 | ||||
-rw-r--r-- | frontends/ast/genrtlil.cc | 14 | ||||
-rw-r--r-- | kernel/bitpattern.h | 10 | ||||
-rw-r--r-- | kernel/consteval.h | 6 | ||||
-rw-r--r-- | kernel/rtlil.cc | 17 | ||||
-rw-r--r-- | kernel/rtlil.h | 4 | ||||
-rw-r--r-- | passes/abc/abc.cc | 38 | ||||
-rw-r--r-- | passes/cmds/show.cc | 4 | ||||
-rw-r--r-- | passes/memory/memory_collect.cc | 10 | ||||
-rw-r--r-- | passes/opt/opt_clean.cc | 13 | ||||
-rw-r--r-- | passes/proc/proc_dff.cc | 2 | ||||
-rw-r--r-- | passes/proc/proc_init.cc | 19 |
17 files changed, 101 insertions, 104 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index 028d1f37a..db49880ae 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -119,10 +119,9 @@ static void autotest(FILE *f, RTLIL::Design *design) if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) continue; RTLIL::SigSpec &signal = (*it4)->signal; - for (size_t i = 0; i < signal.chunks().size(); i++) { - if (signal.chunks()[i].wire == wire) + for (auto &c : signal.chunks()) + if (c.wire == wire) is_clksignal = true; - } } if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { signal_clk[idy("sig", mod->name, wire->name)] = wire->width; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index d0c250790..fc090cfe0 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -68,20 +68,18 @@ struct BlifDumper return cstr_buf.back().c_str(); } - const char *cstr(RTLIL::SigSpec sig) + const char *cstr(RTLIL::SigBit sig) { - log_assert(sig.size() == 1); + if (sig.wire == NULL) + return sig == RTLIL::State::S1 ? "$true" : "$false"; - if (sig.chunks().at(0).wire == NULL) - return sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false"; - - std::string str = RTLIL::unescape_id(sig.chunks().at(0).wire->name); + std::string str = RTLIL::unescape_id(sig.wire->name); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=') str[i] = '?'; - if (sig.chunks().at(0).wire->width != 1) - str += stringf("[%d]", sig.chunks().at(0).offset); + if (sig.wire->width != 1) + str += stringf("[%d]", sig.offset); cstr_buf.push_back(str); return cstr_buf.back().c_str(); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 8f36f4090..a3ae9649e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -314,12 +314,9 @@ struct EdifBackend : public Backend { } } for (auto &it : net_join_db) { - RTLIL::SigSpec sig = it.first; - log_assert(sig.size() == 1); - if (sig.chunks().at(0).wire == NULL) { - if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) - continue; - } + RTLIL::SigBit sig = it.first; + if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) + continue; std::string netname = log_signal(sig); for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') @@ -327,10 +324,10 @@ struct EdifBackend : public Backend { fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); - if (sig.chunks().at(0).wire == NULL) { - if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0) + if (sig.wire == NULL) { + if (sig == RTLIL::State::S0) fprintf(f, " (portRef G (instanceRef GND))\n"); - if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1) + if (sig == RTLIL::State::S1) fprintf(f, " (portRef P (instanceRef VCC))\n"); } fprintf(f, " ))\n"); diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index a312b02ce..e3093e378 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -103,7 +103,7 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint) { if (sig.chunks().size() == 1) { - dump_sigchunk(f, sig.chunks()[0], autoint); + dump_sigchunk(f, sig.chunks().front(), autoint); } else { fprintf(f, "{ "); for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index a4cad5add..b2e472bf3 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -28,23 +28,19 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig) { - if (sig.chunks().size() != 1) -error: + if (!sig.is_fully_const() && !sig.is_wire()) log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig)); conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); - if (sig.chunks()[0].wire == NULL) { + if (sig.is_fully_const()) { celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size())); - constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(), - sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int())); - return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int()); + constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", + sig.size(), sig.as_int(), sig.size(), sig.size(), sig.as_int(), sig.as_int())); + return stringf("CONST_%d_0x%x", sig.size(), sig.as_int()); } - if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width) - goto error; - - return RTLIL::unescape_id(sig.chunks()[0].wire->name); + return RTLIL::unescape_id(sig.as_wire()->name); } struct IntersynthBackend : public Backend { diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 8e894cafd..e548df361 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -25,18 +25,17 @@ #include <string> #include <assert.h> -static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) +static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); - if (s.chunks()[0].wire) { - if (s.chunks()[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset); + if (s.wire) { + if (s.wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.wire->name)); } else { - if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0) + if (s == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1) + else if (s == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -92,7 +91,6 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (auto &sig : port_sigs) { for (int i = 0; i < sig.size(); i++) { RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1); - log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 3d848e823..e74f36abe 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -294,9 +294,9 @@ struct AST_INTERNAL::ProcessGenerator assert(init_lvalue.size() == init_rvalue.size()); int offset = 0; - for (size_t i = 0; i < init_lvalue.chunks().size(); i++) { - RTLIL::SigSpec lhs = init_lvalue.chunks()[i]; - RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue.chunks()[i].width); + for (auto &init_lvalue_c : init_lvalue.chunks()) { + RTLIL::SigSpec lhs = init_lvalue_c; + RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width); sync->actions.push_back(RTLIL::SigSig(lhs, rhs)); offset += lhs.size(); } @@ -398,10 +398,10 @@ struct AST_INTERNAL::ProcessGenerator assert(lvalue.size() == rvalue.size()); int offset = 0; - for (size_t i = 0; i < lvalue.chunks().size(); i++) { - RTLIL::SigSpec lhs = lvalue.chunks()[i]; - RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue.chunks()[i].width); - if (inSyncRule && lvalue.chunks()[i].wire && lvalue.chunks()[i].wire->get_bool_attribute("\\nosync")) + for (auto &lvalue_c : lvalue.chunks()) { + RTLIL::SigSpec lhs = lvalue_c; + RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width); + if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync")) rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); actions.push_back(RTLIL::SigSig(lhs, rhs)); offset += lhs.size(); diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 4f4bc37a0..05b2bbc24 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -35,10 +35,8 @@ struct BitPatternPool if (width > 0) { std::vector<RTLIL::State> pattern(width); for (int i = 0; i < width; i++) { - RTLIL::SigSpec s = sig.extract(i, 1); - assert(s.chunks().size() == 1); - if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.chunks()[0].data.bits[0]; + if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1) + pattern[i] = sig[i].data; else pattern[i] = RTLIL::State::Sa; } @@ -59,9 +57,7 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { - assert(sig.is_fully_const()); - assert(sig.chunks().size() == 1); - bits_t bits = sig.chunks()[0].data.bits; + bits_t bits = sig.as_const().bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/consteval.h b/kernel/consteval.h index 3a8ef44a0..7b1b798c8 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -207,9 +207,9 @@ struct ConstEval if (sig.is_fully_const()) return true; - for (size_t i = 0; i < sig.chunks().size(); i++) - if (sig.chunks()[i].wire != NULL) - undef.append(sig.chunks()[i]); + for (auto &c : sig.chunks()) + if (c.wire != NULL) + undef.append(c); return false; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8e509f360..f741e2a34 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1999,6 +1999,14 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return true; } +bool RTLIL::SigSpec::is_wire() const +{ + cover("kernel.rtlil.sigspec.is_wire"); + + pack(); + return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_; +} + bool RTLIL::SigSpec::is_fully_const() const { cover("kernel.rtlil.sigspec.is_fully_const"); @@ -2104,6 +2112,15 @@ RTLIL::Const RTLIL::SigSpec::as_const() const return RTLIL::Const(); } +RTLIL::Wire *RTLIL::SigSpec::as_wire() const +{ + cover("kernel.rtlil.sigspec.as_wire"); + + pack(); + assert(is_wire()); + return chunks_[0].wire; +} + bool RTLIL::SigSpec::match(std::string pattern) const { cover("kernel.rtlil.sigspec.match"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 68eee46ea..a4b7e8492 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -576,6 +576,7 @@ public: bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } + bool is_wire() const; bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; @@ -585,6 +586,7 @@ public: int as_int() const; std::string as_string() const; RTLIL::Const as_const() const; + RTLIL::Wire *as_wire() const; bool match(std::string pattern) const; @@ -612,7 +614,7 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { assert(sig.size() == 1 && sig.chunks().size() == 1); - *this = SigBit(sig.chunks()[0]); + *this = SigBit(sig.chunks().front()); } struct RTLIL::CaseRule { diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index ba27a3fc6..d25f88c0d 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -709,15 +709,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); module->connections.push_back(conn); continue; } @@ -725,8 +725,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_INV_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -735,9 +735,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_" + c->type.substr(1) + "_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -746,10 +746,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_MUX_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); + cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -759,8 +759,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -777,7 +777,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connections.push_back(conn); continue; @@ -787,8 +787,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -815,9 +815,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks()[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); module->connections.push_back(conn); } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 6b37b7bb1..0a1d584ca 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -177,7 +177,7 @@ struct ShowWorker } if (sig.chunks().size() == 1) { - const RTLIL::SigChunk &c = sig.chunks()[0]; + const RTLIL::SigChunk &c = sig.chunks().front(); if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -200,7 +200,7 @@ struct ShowWorker int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { - const RTLIL::SigChunk &c = sig.chunks()[i]; + const RTLIL::SigChunk &c = sig.chunks().at(i); net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index fec0b407d..3ceb5da36 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -147,8 +147,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index ba0aadc6b..02efabf72 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -104,15 +104,10 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w) return count; } -static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires) +static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires) { - assert(s1.size() == 1); - assert(s2.size() == 1); - assert(s1.chunks().size() == 1); - assert(s2.chunks().size() == 1); - - RTLIL::Wire *w1 = s1.chunks()[0].wire; - RTLIL::Wire *w2 = s2.chunks()[0].wire; + RTLIL::Wire *w1 = s1.wire; + RTLIL::Wire *w2 = s2.wire; if (w1 == NULL || w2 == NULL) return w2 == NULL; @@ -189,7 +184,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1); + RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index a8aba903a..5982fd8e4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -382,7 +382,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks()[0].data, sig, + gen_dff(mod, insig, rstval.as_const(), sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4c9b6bcd2..5976c2162 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -58,16 +58,15 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks().size(); i++) { - if (lhs.chunks()[i].wire == NULL) - continue; - RTLIL::Wire *wire = lhs.chunks()[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); - if (value.size() != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); - log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); - wire->attributes["\\init"] = value.as_const(); - offset += wire->width; + for (auto &lhs_c : lhs.chunks()) { + if (lhs_c.wire != NULL) { + RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width); + if (value.size() != lhs_c.wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value)); + log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value)); + lhs_c.wire->attributes["\\init"] = value.as_const(); + } + offset += lhs_c.width; } } } |