| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | write_verilog: handle the $shift cell. | whitequark | 2018-12-16 | 1 | -0/+29 |
| * | Merge pull request #736 from whitequark/select_assert_list | Clifford Wolf | 2018-12-16 | 2 | -9/+51 |
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| | * | select: print selection if a -assert-* flag causes an error. | whitequark | 2018-12-16 | 1 | -8/+50 |
| | * | write_verilog: add a missing newline. | whitequark | 2018-12-16 | 1 | -1/+1 |
| * | | Rename "fine:" label to "map:" in "synth_ice40" | Clifford Wolf | 2018-12-16 | 1 | -1/+1 |
| * | | Merge pull request #704 from webhat/feature/fix-awk | Clifford Wolf | 2018-12-16 | 1 | -2/+3 |
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| | * | | Using awk rather than gawk | Daniël W. Crompton | 2018-11-19 | 1 | -2/+3 |
| * | | | Merge pull request #738 from smunaut/issue_737 | Clifford Wolf | 2018-12-16 | 1 | -19/+29 |
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| | * | | | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| * | | | | Merge pull request #735 from daveshah1/trifixes | Clifford Wolf | 2018-12-16 | 1 | -3/+4 |
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| | * | | | | deminout: Consider $tribuf cells | David Shah | 2018-12-12 | 1 | -2/+2 |
| | * | | | | deminout: Don't demote constant-driven inouts to inputs | David Shah | 2018-12-12 | 1 | -1/+2 |
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| * | | | | Merge pull request #739 from whitequark/patch-1 | Clifford Wolf | 2018-12-16 | 1 | -0/+7 |
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| | * | | | | Add .editorconfig file. | whitequark | 2018-12-16 | 1 | -0/+7 |
| * | | | | | Fix equiv_opt indenting | Clifford Wolf | 2018-12-16 | 1 | -139/+129 |
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| * | | | | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 6 | -27/+173 |
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| | * | | | | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 4 | -6/+7 |
| | * | | | | equiv_opt: new command, for verifying optimization passes. | whitequark | 2018-12-07 | 4 | -24/+169 |
| * | | | | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata | Clifford Wolf | 2018-12-16 | 1 | -0/+17 |
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| | * | | | | | memory_bram: Fix initdata bit order after shuffling | Graham Edgecombe | 2018-12-11 | 1 | -0/+17 |
| * | | | | | | Merge pull request #730 from smunaut/ffssr_dont_touch | Clifford Wolf | 2018-12-16 | 1 | -0/+3 |
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| | * | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass | Sylvain Munaut | 2018-12-08 | 1 | -0/+3 |
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| * | | | | | | Merge pull request #729 from whitequark/write_verilog_initial | Clifford Wolf | 2018-12-16 | 1 | -0/+2 |
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| | * | | | | | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 |
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| * | | | | | | Merge pull request #725 from olofk/ram4k-init | Clifford Wolf | 2018-12-16 | 1 | -0/+19 |
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| | * | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys | Olof Kindgren | 2018-12-06 | 1 | -0/+19 |
| * | | | | | | | Merge pull request #714 from daveshah1/abc_preserve_naming | Clifford Wolf | 2018-12-16 | 1 | -29/+51 |
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| | * | | | | | | | abc: Preserve naming through ABC using 'dress' command | David Shah | 2018-12-06 | 1 | -29/+51 |
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| * | | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gates | Clifford Wolf | 2018-12-16 | 1 | -0/+4 |
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| | * | | | | | | | synth_ice40: split `map_gates` off `fine`. | whitequark | 2018-12-06 | 1 | -0/+4 |
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| * | | | | | | | Merge pull request #722 from whitequark/rename_src | Clifford Wolf | 2018-12-16 | 1 | -0/+50 |
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| | * | | | | | | | rename: add -src, for inferring names from source locations. | whitequark | 2018-12-05 | 1 | -0/+50 |
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| * | | | | | | | Merge pull request #720 from whitequark/master | Clifford Wolf | 2018-12-16 | 2 | -2/+2 |
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| | * | | | | | | lut2mux: handle 1-bit INIT constant in $lut cells. | whitequark | 2018-12-05 | 1 | -1/+1 |
| | * | | | | | | opt_lut: simplify type conversion. NFC. | whitequark | 2018-12-05 | 1 | -1/+1 |
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| * | | | / / | Add yosys-smtbmc support for btor witness | Clifford Wolf | 2018-12-10 | 1 | -15/+100 |
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| * | | | | | Add "yosys-smtbmc --btorwit" skeleton | Clifford Wolf | 2018-12-08 | 1 | -1/+19 |
| * | | | | | Fix btor init value handling | Clifford Wolf | 2018-12-08 | 1 | -9/+13 |
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| * | | | | Merge pull request #727 from whitequark/opt_lut | David Shah | 2018-12-07 | 3 | -5/+50 |
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| | * | | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 3 | -0/+26 |
| | * | | | opt_lut: show original truth table for both cells. | whitequark | 2018-12-07 | 1 | -2/+3 |
| | * | | | opt_lut: add -limit option, for debugging misoptimizations. | whitequark | 2018-12-07 | 1 | -3/+21 |
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| * | | | Add missing .gitignore | Clifford Wolf | 2018-12-06 | 1 | -0/+8 |
| * | | | Bugfix in opt_expr handling of a<0 and a>=0 | Clifford Wolf | 2018-12-06 | 1 | -1/+1 |
| * | | | Verific updates | Clifford Wolf | 2018-12-06 | 2 | -54/+1 |
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| * | | Merge pull request #709 from smunaut/issue_708 | Clifford Wolf | 2018-12-05 | 1 | -1/+1 |
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| | * | | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 |
| * | | | Merge pull request #718 from whitequark/gate2lut | Clifford Wolf | 2018-12-05 | 12 | -4/+151 |
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| | * | | | synth_ice40: add -noabc option, to use built-in LUT techmapping. | whitequark | 2018-12-05 | 1 | -2/+16 |
| | * | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 10 | -0/+133 |
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index : iCE40/yosys | |
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