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| author | Sylvain Munaut <tnt@246tNt.com> | 2018-11-24 18:49:23 +0100 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2018-11-24 18:49:23 +0100 |
| commit | 86ce43999eaed10c3b9d141bb2f66bf98ad45eb6 (patch) | |
| tree | ea2c9ab46c74f01f79828ea4fae9f32feefef677 | |
| parent | ab97eddee9b0ea0a772660731fe4c3270d2564e5 (diff) | |
| download | yosys-86ce43999eaed10c3b9d141bb2f66bf98ad45eb6.tar.gz yosys-86ce43999eaed10c3b9d141bb2f66bf98ad45eb6.tar.bz2 yosys-86ce43999eaed10c3b9d141bb2f66bf98ad45eb6.zip | |
Make return value of $clog2 signed
As per Verilog 2005 - 17.11.1.
Fixes #708
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bb4c9735d..55abe165f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:; if (arg_value.bits.at(i) == RTLIL::State::S1) result = i + 1; - newNode = mkconst_int(result, false); + newNode = mkconst_int(result, true); goto apply_newNode; } |