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| * | | | | | | | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-272-12/+23
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| * | | | | | | | Fix spacingEddie Hung2020-02-272-68/+68
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| * | | | | | | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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| * | | | | | | | Cleanup testsEddie Hung2020-02-272-1/+1
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| * | | | | | | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
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| * | | | | | | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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| * | | | | | | | abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
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| * | | | | | | | write_xaiger: add comment about arrival times of flop outputsEddie Hung2020-02-271-0/+1
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| * | | | | | | | abc9_ops: demote lack of box timing info to warningEddie Hung2020-02-271-2/+4
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| * | | | | | | | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-276-651/+530
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| * | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-272-25/+22
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| * | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-273-97/+65
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| * | | | | | | | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-272-70/+214
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| * | | | | | | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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| * | | | | | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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| * | | | | | | | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
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| * | | | | | | | Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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| * | | | | | | | Update simple_abc9 testsEddie Hung2020-02-273-5/+8
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| * | | | | | | | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-274-104/+114
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| * | | | | | | | ice40: specify fixesEddie Hung2020-02-273-66/+66
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| * | | | | | | | abc9_ops: sort LUT delays to be ascendingEddie Hung2020-02-271-1/+4
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| * | | | | | | | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
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| * | | | | | | | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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| * | | | | | | | Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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| * | | | | | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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| * | | | | | | | abc9_ops: output LUT areaEddie Hung2020-02-271-6/+6
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| * | | | | | | | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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| * | | | | | | | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTsEddie Hung2020-02-271-18/+33
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| * | | | | | | | Fix commented out specify statementEddie Hung2020-02-271-6/+6
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| * | | | | | | | xilinx: improve specify functionalityEddie Hung2020-02-278-466/+547
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| * | | | | | | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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| * | | | | | | | xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-273-347/+670
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| * | | | | | | | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-278-466/+268
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| * | | | | | | | abc9_ops: assert on $specify2 propertiesEddie Hung2020-02-271-0/+3
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| * | | | | | | | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-273-51/+50
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| * | | | | | | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-274-10/+200
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* | | | | | | | | Merge pull request #1729 from rqou/coolrunner2N. Engelhardt2020-03-023-109/+443
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | coolrunner2 buffer cell insertion fixes
| * | | | | | | | | coolrunner2: Attempt to give wires/cells more meaningful namesR. Ou2020-03-022-23/+66
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| * | | | | | | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gatesR. Ou2020-03-021-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
| * | | | | | | | | coolrunner2: Fix packed register+input buffer insertionR. Ou2020-03-021-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads.
| * | | | | | | | | coolrunner2: Insert many more required feedthrough cellsR. Ou2020-03-013-102/+215
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* | | | | | | | | Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2Eddie Hung2020-02-291-11/+11
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
| * | | | | | | | | ystests: fix write_smt2_write_smt2_cyclic_dependency_failEddie Hung2020-02-281-11/+11
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* | | | | | | | | | Merge pull request #1726 from YosysHQ/eddie/fix1710Eddie Hung2020-02-282-9/+52
|\ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / |/| | | | | | | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary branch
| * | | | | | | | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-272-9/+52
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* / / / / / / / / Comment out log()Eddie Hung2020-02-271-1/+1
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* | | | | | | | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-274-97/+519
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Improve CoolRunner-II optimization by using extract_counter pass
| * | | | | | | | coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
| * | | | | | | | extract_counter: Implement extracting up countersR. Ou2020-02-171-65/+247
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| * | | | | | | | extract_counter: Add support for inverted clock enableR. Ou2020-02-171-8/+28
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