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* Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Merge pull request #746 from Icenowy/anlogic-dramClifford Wolf2018-12-175-1/+355
|\ | | | | Support for DRAM inferring on Anlogic FPGAs
| * anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
| * Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #742 from whitequark/changelogClifford Wolf2018-12-171-0/+7
|\ \ | | | | | | Update CHANGELOG to mention my improvements
| * | Update CHANGELOG.whitequark2018-12-161-0/+7
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* | | Merge pull request #741 from whitequark/ilang_slice_sigspecClifford Wolf2018-12-171-10/+6
|\ \ \ | | | | | | | | read_ilang: allow slicing all sigspecs, not just wires
| * | | read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
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* | | Merge pull request #744 from whitequark/write_verilog_$shiftClifford Wolf2018-12-171-0/+29
|\ \ \ | |_|/ |/| | write_verilog: handle the $shift cell
| * | write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* | Merge pull request #745 from YosysHQ/revert-714-abc_preserve_namingClifford Wolf2018-12-161-51/+29
|\ \ | |/ |/| Revert "Proof-of-concept: preserve naming through ABC using dress"
| * Revert "Proof-of-concept: preserve naming through ABC using dress"Clifford Wolf2018-12-161-51/+29
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* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-162-9/+51
|\ | | | | select: print selection if a -assert-* flag causes an error
| * select: print selection if a -assert-* flag causes an error.whitequark2018-12-161-8/+50
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
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* | Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #704 from webhat/feature/fix-awkClifford Wolf2018-12-161-2/+3
|\ \ | | | | | | Using awk rather than gawk
| * | Using awk rather than gawkDaniël W. Crompton2018-11-191-2/+3
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* | | Merge pull request #738 from smunaut/issue_737Clifford Wolf2018-12-161-19/+29
|\ \ \ | | | | | | | | verilog_parser: Properly handle recursion when processing attributes
| * | | verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | Merge pull request #735 from daveshah1/trifixesClifford Wolf2018-12-161-3/+4
|\ \ \ \ | | | | | | | | | | deminout fixes
| * | | | deminout: Consider $tribuf cellsDavid Shah2018-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | deminout: Don't demote constant-driven inouts to inputsDavid Shah2018-12-121-1/+2
| |/ / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #739 from whitequark/patch-1Clifford Wolf2018-12-161-0/+7
|\ \ \ \ | | | | | | | | | | Add .editorconfig file
| * | | | Add .editorconfig file.whitequark2018-12-161-0/+7
| | | | | | | | | | | | | | | See https://editorconfig.org/ for details.
* | | | | Fix equiv_opt indentingClifford Wolf2018-12-161-139/+129
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-166-27/+173
|\ \ \ \ | | | | | | | | | | equiv_opt: new command, for verifying optimization passes
| * | | | equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-074-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * | | | equiv_opt: new command, for verifying optimization passes.whitequark2018-12-074-24/+169
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* | | | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdataClifford Wolf2018-12-161-0/+17
|\ \ \ \ \ | | | | | | | | | | | | memory_bram: Fix initdata bit order after shuffling
| * | | | | memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* | | | | | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ \ \ \ \ | | | | | | | | | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | | | | | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | | | | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | write_verilog: correctly map RTLIL `sync init`
| * | | | | | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | | | | | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ \ \ \ \ | | | | | | | | | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
| * | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In an initial statement, blocking assignments are normally used and e.g. verilator throws a warning if non-blocking ones are used. Yosys cannot however properly resolve the interdependencies if blocking assignments are used in the initialization of SB_RAM_40_4K and thus this has been used. This patch will change to use non-blocking assignments only for yosys
* | | | | | | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | | | | | | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | Merge pull request #723 from whitequark/synth_ice40_map_gatesClifford Wolf2018-12-161-0/+4
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | synth_ice40: split `map_gates` off `fine`
| * | | | | | | synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* | | | | | | Merge pull request #722 from whitequark/rename_srcClifford Wolf2018-12-161-0/+50
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | rename: add -src, for inferring names from source locations
| * | | | | | | rename: add -src, for inferring names from source locations.whitequark2018-12-051-0/+50
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* | | | | | | Merge pull request #720 from whitequark/masterClifford Wolf2018-12-162-2/+2
|\ \ \ \ \ \ \ | |_|_|_|_|/ / |/| | | | | | lut2mux: handle 1-bit INIT constant in $lut cells
| * | | | | | lut2mux: handle 1-bit INIT constant in $lut cells.whitequark2018-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case.
| * | | | | | opt_lut: simplify type conversion. NFC.whitequark2018-12-051-1/+1
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* | | | / / Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
| |_|_|/ / |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
| |_|/ / |/| | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #727 from whitequark/opt_lutDavid Shah2018-12-073-5/+50
|\ \ \ \ | |_|/ / |/| | | opt_lut: leave intact LUTs with cascade feeding module outputs
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