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* Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adderEddie Hung2019-08-1020-180/+180
|\ | | | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
| * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-1020-180/+180
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* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-1069-414/+405
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-0731-127/+127
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| * RTLIL::S{0,1} -> State::S{0,1} for headersEddie Hung2019-08-075-40/+40
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| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-0715-86/+86
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| * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-0719-383/+879
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| * | Remove std:: namespaceEddie Hung2019-08-071-5/+5
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| * | 'make clean' to not remove anything abcEddie Hung2019-08-071-1/+1
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| * | stoi -> atoiEddie Hung2019-08-0741-121/+121
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| * | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-062-2/+2
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| * | Fix typosEddie Hung2019-08-063-9/+9
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| * | Fix spacingEddie Hung2019-08-061-3/+3
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| * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-0636-109/+109
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| * | Use IdString::begins_with()Eddie Hung2019-08-065-28/+30
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| * | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-062-21/+21
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| * | Use State::S{0,1}Eddie Hung2019-08-0610-19/+19
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| * | Make liberal use of IdString.in()Eddie Hung2019-08-0618-51/+45
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| * | Cleanup opt_expr.ccEddie Hung2019-08-061-35/+30
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* | | Merge pull request #1261 from YosysHQ/clifford/verific_initClifford Wolf2019-08-103-12/+74
|\ \ \ | | | | | | | | Automatically prune init attributes in verific front-end
| * | | Automatically prune init attributes in verific front-end, fixes #1237Clifford Wolf2019-08-073-12/+74
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cellClifford Wolf2019-08-101-1/+1
|\ \ \ \ | | | | | | | | | | FIRRTL error on unsupported cell
| * \ \ \ Merge branch 'master' into firrtl_err_on_unsupported_cellJim Lawson2019-08-0764-489/+1315
| |\ \ \ \ | | | |_|/ | | |/| | | | | | | | | | | | # Conflicts: # backends/firrtl/firrtl.cc
| * | | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ↵Jim Lawson2019-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | backend.
* | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
|\ \ \ \ \ | | | | | | | | | | | | Add a few comments to document $alu and $lcu
| * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| * | | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| * | | | | Add more commentsEddie Hung2019-08-091-4/+18
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| * | | | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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* | | | | | Merge pull request #1272 from mmicko/travis_fixClifford Wolf2019-08-101-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Propagate parameters for Travis build
| * | | | | | ABC requires it like thisMiodrag Milanovic2019-08-091-1/+1
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| * | | | | | Propagate parameters for Travis buildMiodrag Milanovic2019-08-091-1/+1
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* | | | | | | Merge pull request #1274 from YosysHQ/eddie/fix_1271Clifford Wolf2019-08-101-0/+1
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
| * | | | | | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithroEddie Hung2019-08-091-0/+1
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* | | | | | | Merge pull request #1276 from YosysHQ/clifford/fix1273Clifford Wolf2019-08-101-15/+54
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
| * | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵Clifford Wolf2019-08-091-15/+54
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Merge pull request #1267 from whitequark/proc_prune-fix-1243whitequark2019-08-091-9/+7
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | proc_prune: fix handling of exactly identical assigns
| * | | | | | proc_prune: fix handling of exactly identical assigns.whitequark2019-08-081-9/+7
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
* | | | | | Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
|\ \ \ \ \ \ | | | | | | | | | | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
| * | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
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* | | | | | Merge pull request #1266 from YosysHQ/eddie/ice40_full_adderEddie Hung2019-08-0820-180/+180
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
| * | | | | Remove dump callEddie Hung2019-08-071-1/+0
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| * | | | | Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
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| * | | | | Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
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| * | | | | Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
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| * | | | | Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
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| * | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-072-3/+1
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| * | | | | Update CHANGELOGEddie Hung2019-08-071-0/+2
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| * | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-076-10/+128
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| * | | | | Add testEddie Hung2019-08-071-1/+10
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