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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 19:08:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 19:08:33 -0700 |
| commit | ee7c970367c68fe1a02a237ed01f2845a03cf9b2 (patch) | |
| tree | 8ef4e5a13318311f02031b2608bc71351e4ded78 | |
| parent | 234fcf1724941b5c4fa77cc0359d339ddd36aeb3 (diff) | |
| download | yosys-ee7c970367c68fe1a02a237ed01f2845a03cf9b2.tar.gz yosys-ee7c970367c68fe1a02a237ed01f2845a03cf9b2.tar.bz2 yosys-ee7c970367c68fe1a02a237ed01f2845a03cf9b2.zip | |
IdString::str().substr() -> IdString::substr()
| -rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index e947125bf..b27780fae 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2319,7 +2319,7 @@ skip_dynamic_range_lvalue_expansion:; if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0) { AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone()); - cell_arg->str = RTLIL::escape_id(attr.first.str().substr(strlen("\\via_celltype_defparam_"))); + cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_"))); cell->children.push_back(cell_arg); } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index ff5c3b6a1..1319225ff 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -203,7 +203,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int idx = std::stoi(cell->type.substr(pos_idx + 1, pos_num)); int num = std::stoi(cell->type.substr(pos_num + 1, pos_type)); array_cells[cell] = std::pair<int, int>(idx, num); - cell->type = cell->type.str().substr(pos_type + 1); + cell->type = cell->type.substr(pos_type + 1); } dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule; dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule; |