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| author | whitequark <whitequark@whitequark.org> | 2019-08-09 17:10:46 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-09 17:10:46 +0000 |
| commit | 39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3 (patch) | |
| tree | bf00c07c3cc9d785331ef12392e85ae00b3b21d0 | |
| parent | ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76 (diff) | |
| parent | 0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8 (diff) | |
| download | yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.tar.gz yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.tar.bz2 yosys-39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3.zip | |
Merge pull request #1267 from whitequark/proc_prune-fix-1243
proc_prune: fix handling of exactly identical assigns
| -rw-r--r-- | passes/proc/proc_prune.cc | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index b47ee79c2..d4aee9df0 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -65,8 +65,7 @@ struct PruneWorker pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected); assigned.insert(sw_assigned.begin(), sw_assigned.end()); } - pool<RTLIL::SigSig> remove; - for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) { + for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) { RTLIL::SigSpec lhs = sigmap(it->first); bool redundant = true; for (auto &bit : lhs) { @@ -75,9 +74,10 @@ struct PruneWorker break; } } + bool remove = false; if (redundant) { removed_count++; - remove.insert(*it); + remove = true; } else { if (root) { bool promotable = true; @@ -99,7 +99,7 @@ struct PruneWorker } promoted_count++; module->connect(conn); - remove.insert(*it); + remove = true; } } for (auto &bit : lhs) @@ -109,11 +109,9 @@ struct PruneWorker if (bit.wire) affected.insert(bit); } - } - for (auto it = cs->actions.begin(); it != cs->actions.end(); ) { - if (remove[*it]) { - it = cs->actions.erase(it); - } else it++; + if (remove) + cs->actions.erase((it++).base() - 1); + else it++; } return assigned; } |