Make liberal use of IdString.in()

18 files changed, 45 insertions, 51 deletions

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index ddd680782..db849882e 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -601,7 +601,7 @@ struct Smt2Worker
 			if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false);
 			if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false);
 
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				int width = GetSize(cell->getPort("\\Y"));
 				std::string processed_expr = get_bv(cell->getPort("\\A"));
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 776f4eacb..9a797b535 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -949,7 +949,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffe")
+	if (cell->type.in("$dff", "$adff", "$dffe"))
 	{
 		RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
 		bool pol_clk, pol_arst = false, pol_en = false;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ba8472ec1..42c65143d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -940,7 +940,7 @@ namespace {
 				return;
 			}
 
-			if (cell->type == "$logic_and" || cell->type == "$logic_or") {
+			if (cell->type.in("$logic_and", "$logic_or")) {
 				param_bool("\\A_SIGNED");
 				param_bool("\\B_SIGNED");
 				port("\\A", param("\\A_WIDTH"));
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index c34d0c15c..1610ec751 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -50,7 +50,7 @@ struct FsmExpand
 		if (full_mode || cell->type == "$_MUX_")
 			return true;
 
-		if (cell->type == "$mux" || cell->type == "$pmux")
+		if (cell->type.in("$mux", "$pmux"))
 			if (cell->getPort("\\A").size() < 2)
 				return true;
 
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 32b97f27a..be4b3c100 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -262,7 +262,7 @@ struct MemoryDffWorker
 				mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
 				mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
 			}
-			if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
+			if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
 				SigSpec sig_a = cell->getPort("\\A");
 				SigSpec sig_y = cell->getPort("\\Y");
 				if (cell->type == "$not")
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 172afe0cb..eb912cfd4 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -155,7 +155,7 @@ struct MemoryShareWorker
 		{
 			bool ignore_data_port = false;
 
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
 				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
@@ -173,7 +173,7 @@ struct MemoryShareWorker
 				continue;
 			}
 
-			if ((cell->type == "$memwr" || cell->type == "$memrd") &&
+			if (cell->type.in("$memwr", "$memrd") &&
 					cell->parameters.at("\\MEMID").decode_string() == memid)
 				ignore_data_port = true;
 
@@ -690,7 +690,7 @@ struct MemoryShareWorker
 					sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
 			}
 
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
 				for (int i = 0; i < int(sig_y.size()); i++)
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 7567d4657..8964171e6 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -94,8 +94,8 @@ struct OptMergeWorker
 		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
 		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
-		if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
-				cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
+		if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
+				"$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
 			alt_conn = *conn;
 			if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
 				alt_conn["\\A"] = conn->at("\\B");
@@ -103,13 +103,13 @@ struct OptMergeWorker
 			}
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
+		if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort();
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
+		if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort_and_unify();
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 6511e091b..4b96fe524 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -84,7 +84,7 @@ struct OptMuxtreeWorker
 		//	.const_deactivated
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				RTLIL::SigSpec sig_a = cell->getPort("\\A");
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index be6ac2d30..d712736c1 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -71,7 +71,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
 		pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
 	} else
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr") {
+	if (cell->type.in("$dffsr", "$dlatchsr")) {
 		pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0;
 		pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0;
 	} else
@@ -137,7 +137,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr")
+	if (cell->type.in("$dffsr", "$dlatchsr"))
 	{
 		cell->setParam("\\WIDTH", GetSize(sig_d));
 		cell->setPort("\\SET", sig_set);
@@ -624,7 +624,7 @@ struct OptRmdffPass : public Pass {
 						}
 				}
 
-				if (cell->type == "$mux" || cell->type == "$pmux") {
+				if (cell->type.in("$mux", "$pmux")) {
 					if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
 						mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
 					continue;
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index c85c27427..7f66f749f 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -376,13 +376,13 @@ struct ShareWorker
 				continue;
 			}
 
-			if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
+			if (cell->type.in("$mul", "$div", "$mod")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
 					shareable_cells.insert(cell);
 				continue;
 			}
 
-			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
+			if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
 					shareable_cells.insert(cell);
 				continue;
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index d069f152a..c606deb88 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -55,7 +55,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
 			return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 		}
 
-		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) {
+		if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) {
 			if (cell->getPort("\\A").is_fully_const()) {
 				if (!cell->getPort("\\A").as_bool())
 					polarity = !polarity;
@@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
 			}
 		}
 
-		if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) {
+		if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) {
 			if (cell->getPort("\\A").is_fully_const()) {
 				if (cell->getPort("\\A").as_bool())
 					polarity = !polarity;
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 41a05c619..73f63a4e1 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
 
 void extract_cell(RTLIL::Cell *cell, bool keepff)
 {
-	if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+	if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
 	{
 		if (clk_polarity != (cell->type == "$_DFF_P_"))
 			return;
@@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 		goto matching_dff;
 	}
 
-	if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+	if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
 	{
-		if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
+		if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
 			return;
-		if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
+		if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
 			return;
 		if (clk_sig != assign_map(cell->getPort("\\C")))
 			return;
@@ -1824,15 +1824,15 @@ struct AbcPass : public Pass {
 					}
 				}
 
-				if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+				if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
 				{
 					key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
 				}
 				else
-				if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+				if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
 				{
-					bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
-					bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
+					bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
+					bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
 					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
 				}
 				else
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 658bb1225..34919cf07 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass {
 					}
 				}
 
-				if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+				if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
 				{
 					key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
 				}
 				else
-				if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+				if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
 				{
-					bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
-					bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
+					bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
+					bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
 					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
 				}
 				else
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index 35df2ff79..2423676cb 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -66,7 +66,7 @@ struct AigmapPass : public Pass {
 			{
 				Aig aig(cell);
 
-				if (cell->type == "$_AND_" || cell->type == "$_NOT_")
+				if (cell->type.in("$_AND_", "$_NOT_"))
 					aig.name.clear();
 
 				if (nand_mode && cell->type == "$_NAND_")
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 47d0ff416..142d12bdc 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -85,7 +85,7 @@ struct DeminoutPass : public Pass {
 
 					if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
 					{
-						bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf");
+						bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
 
 						if (!tribuf) {
 							for (auto &c : cell->connections()) {
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 7e1040963..44bc14628 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -52,13 +52,13 @@ struct Dff2dffeWorker
 		}
 
 		for (auto cell : module->cells()) {
-			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
+			if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
 				RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
 				for (int i = 0; i < GetSize(sig_y); i++)
 					bit2mux[sig_y[i]] = cell_int_t(cell, i);
 			}
 			if (direct_dict.empty()) {
-				if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+				if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
 					dff_cells.push_back(cell);
 			} else {
 				if (direct_dict.count(cell->type))
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f3da80c66..6c70ffd4f 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_b = cell->getPort("\\B");
 	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 	bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
-	bool is_ne = cell->type == "$ne" || cell->type == "$nex";
+	bool is_ne = cell->type.in("$ne", "$nex");
 
 	RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
 	RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 48da0d8ad..68cc5d568 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
 			dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
+                            "\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
 				{
 					if (cell->hasPort("\\PRE"))
 						special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
 			pool<SigBit> sig_fed_by_ff;
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+                            "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					auto output = sigmap(cell->getPort("\\Q")[0]);
 					sig_fed_by_ff.insert(output);
@@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
 			// Look at all the FF inputs
 			for (auto cell : module->selected_cells())
 			{
-				if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
-					cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
-					cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
-					cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
+				if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
+                            "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
 				{
 					SigBit input;
-					if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+					if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 						input = sigmap(cell->getPort("\\T")[0]);
 					else
 						input = sigmap(cell->getPort("\\D")[0]);
@@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
 						xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
 						xor_cell->setPort("\\OUT", xor_to_ff_wire);
 
-						if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
+						if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
 							cell->setPort("\\T", xor_to_ff_wire);
 						else
 							cell->setPort("\\D", xor_to_ff_wire);