Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | | | | Merge pull request #1199 from mmicko/extract_fa_fix | Clifford Wolf | 2019-07-16 | 1 | -2/+2 | |
|\ \ \ \ | |/ / / |/| | | | Fix check logic in extract_fa | |||||
| * | | | Fix check logic in extract_fa | Miodrag Milanovic | 2019-07-16 | 1 | -2/+2 | |
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* | | | Merge pull request #1196 from YosysHQ/eddie/fix1178 | Eddie Hung | 2019-07-15 | 1 | -5/+12 | |
|\ \ \ | | | | | | | | | Fix different synth results between with and without debug output "-g" | |||||
| * | | | Revert "Add log_checkpoint function and use it in opt_muxtree" | Eddie Hung | 2019-07-15 | 3 | -9/+0 | |
| | | | | | | | | | | | | | | | | This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574. | |||||
| * | | | Revert "Fix first divergence in #1178" | Eddie Hung | 2019-07-15 | 1 | -5/+1 | |
| | | | | | | | | | | | | | | | | This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de. | |||||
| * | | | Merge branch 'master' into eddie/fix1178 | Eddie Hung | 2019-07-15 | 26 | -93/+1204 | |
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| * | | | | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ↵ | Clifford Wolf | 2019-07-15 | 1 | -6/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes #1178 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Add log_checkpoint function and use it in opt_muxtree | Clifford Wolf | 2019-07-15 | 3 | -0/+9 | |
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | Fix first divergence in #1178 | Eddie Hung | 2019-07-09 | 1 | -1/+5 | |
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* | | | | | Merge pull request #1189 from YosysHQ/eddie/fix1151 | Clifford Wolf | 2019-07-15 | 1 | -0/+4 | |
|\ \ \ \ \ | | | | | | | | | | | | | Error out if enable > dbits in memory_bram file | |||||
| * | | | | | Error out if enable > dbits | Eddie Hung | 2019-07-13 | 1 | -0/+4 | |
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* | | | | | Merge pull request #1190 from YosysHQ/eddie/fix_1099 | Clifford Wolf | 2019-07-15 | 1 | -4/+8 | |
|\ \ \ \ \ | | | | | | | | | | | | | extract_fa to return nothing more gracefully | |||||
| * | | | | | If ConstEval fails do not log_abort() but return gracefully | Eddie Hung | 2019-07-13 | 1 | -4/+8 | |
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* | | | | | Merge pull request #1191 from whitequark/opt_lut-log_debug | Clifford Wolf | 2019-07-15 | 1 | -56/+38 | |
|\ \ \ \ \ | | | | | | | | | | | | | Make opt_lut less chatty | |||||
| * | | | | | opt_lut: make less chatty. | whitequark | 2019-07-13 | 1 | -56/+38 | |
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* | | | | | Merge pull request #1195 from Roman-Parise/master | Clifford Wolf | 2019-07-15 | 1 | -1/+1 | |
|\ \ \ \ \ | | | | | | | | | | | | | Updated FreeBSD dependencies in README.md | |||||
| * | | | | | Updated FreeBSD dependencies in README.md | Roman-Parise | 2019-07-14 | 1 | -1/+1 | |
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* | | | | | Merge pull request #1197 from nakengelhardt/handle-setrlimit-fail | Clifford Wolf | 2019-07-15 | 1 | -1/+5 | |
|\ \ \ \ \ | |/ / / / |/| | | | | smt: handle failure of setrlimit syscall | |||||
| * | | | | smt: handle failure of setrlimit syscall | N. Engelhardt | 2019-07-15 | 1 | -1/+5 | |
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* | | | | Merge pull request #1194 from cr1901/miss-semi | Eddie Hung | 2019-07-14 | 1 | -2/+2 | |
|\ \ \ \ | |/ / / |/| | | | Fix missing semicolon in Windows-specific code in aigerparse.cc. | |||||
| * | | | Fix missing semicolon in Windows-specific code in aigerparse.cc. | William D. Jones | 2019-07-14 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net> | |||||
* | | | | Merge pull request #1183 from whitequark/ice40-always-relut | Clifford Wolf | 2019-07-12 | 1 | -11/+5 | |
|\ \ \ \ | |_|_|/ |/| | | | synth_ice40: switch -relut to be always on | |||||
| * | | | synth_ice40: switch -relut to be always on. | whitequark | 2019-07-11 | 1 | -10/+4 | |
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| * | | | synth_ice40: fix help text typo. NFC. | whitequark | 2019-07-11 | 1 | -1/+1 | |
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* | | | Merge pull request #1182 from koriakin/xc6s-bram | Eddie Hung | 2019-07-11 | 9 | -8/+598 | |
|\ \ \ | | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | |||||
| * | | | synth_xilinx: Initial Spartan 6 block RAM inference support. | Marcin Kościelnicki | 2019-07-11 | 9 | -8/+598 | |
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* | | | Merge pull request #1185 from koriakin/xc-ff-init-vals | Eddie Hung | 2019-07-11 | 2 | -6/+6 | |
|\ \ \ | | | | | | | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. | |||||
| * | | | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵ | Marcin Kościelnicki | 2019-07-11 | 2 | -6/+6 | |
| |/ / | | | | | | | | | | ISE/Vivado. | |||||
* / / | Enable &mfs for abc9, even if it only currently works for ice40 | Eddie Hung | 2019-07-11 | 1 | -1/+1 | |
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* | | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 | |
|\ \ | | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ? | |||||
| * | | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 | |
| | | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog. | |||||
* | | | Merge pull request #1179 from whitequark/attrmap-proc | Clifford Wolf | 2019-07-11 | 1 | -0/+19 | |
|\ \ \ | | | | | | | | | attrmap: also consider process, switch and case attributes | |||||
| * | | | attrmap: also consider process, switch and case attributes. | whitequark | 2019-07-10 | 1 | -0/+19 | |
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* | | | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime | Eddie Hung | 2019-07-10 | 3 | -6/+15 | |
|\ \ \ | | | | | | | | | Error out if -abc9 and -retime specified | |||||
| * | | | Error out if -abc9 and -retime specified | Eddie Hung | 2019-07-10 | 3 | -6/+15 | |
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* | | | Merge pull request #1148 from YosysHQ/xc7mux | Eddie Hung | 2019-07-10 | 7 | -49/+415 | |
|\ \ \ | | | | | | | | | synth_xilinx to infer wide multiplexers using new '-widemux <min>' option | |||||
| * | | | Add some spacing | Eddie Hung | 2019-07-10 | 1 | -9/+9 | |
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| * | | | Add some ASCII art explaining mux decomposition | Eddie Hung | 2019-07-10 | 1 | -0/+21 | |
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| * | | | Call muxpack and pmux2shiftx before cmp2lut | Eddie Hung | 2019-07-09 | 1 | -9/+12 | |
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| * | | | Restore opt_clean back to original place | Eddie Hung | 2019-07-09 | 1 | -2/+1 | |
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| * | | | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 | Eddie Hung | 2019-07-09 | 1 | -0/+2 | |
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| * | | | Extend using A[1] to preserve don't care | Eddie Hung | 2019-07-09 | 1 | -1/+9 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux | Eddie Hung | 2019-07-09 | 2 | -4/+9 | |
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| * | | | | Extend during mux decomposition with 1'bx | Eddie Hung | 2019-07-09 | 1 | -24/+3 | |
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| * | | | | Fix typo and comments | Eddie Hung | 2019-07-09 | 1 | -4/+4 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-07-09 | 16 | -79/+348 | |
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| * | | | | synth_xilinx to call commands of synth -coarse directly | Eddie Hung | 2019-07-09 | 1 | -3/+20 | |
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| * | | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" | Eddie Hung | 2019-07-09 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031. | |||||
| * | | | | Fix spacing | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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| * | | | | Fix spacing | Eddie Hung | 2019-07-09 | 1 | -1/+1 | |
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