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* Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
* Fix build error with clangRuben Undheim2018-10-121-1/+1
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
* Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
* Merge pull request #651 from ARandomOWL/stdcells_fixClifford Wolf2018-10-051-1/+1
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| * Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-041-1/+1
* | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
* | Merge pull request #654 from mithro/patch-1Clifford Wolf2018-10-051-1/+1
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| * | Fix misspelling in issue_template.mdTim Ansell2018-10-041-1/+1
* | | Fix compiler warning in verific.ccClifford Wolf2018-10-051-0/+2
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* | Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
* | Merge pull request #650 from mithro/patch-1Clifford Wolf2018-10-041-0/+1
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| * | xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* | Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
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| * | ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
* | | Merge pull request #646 from tomverbeure/issue594Clifford Wolf2018-10-021-1/+2
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| * | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
* | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
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| * | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
* | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-281-4/+4
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| * | Update to v2 YosysVS templateClifford Wolf2018-09-281-4/+4
* | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
* | | Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
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* | Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rcClifford Wolf2018-09-231-11/+11
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| * | added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
* | | Update CHANGELOGClifford Wolf2018-09-231-2/+35
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* | Update CHANGLELOGClifford Wolf2018-09-211-5/+27
* | Update ChangelogClifford Wolf2018-09-211-1/+54
* | Merge pull request #633 from mmicko/masterClifford Wolf2018-09-193-1/+14
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| * | Fix Cygwin build and document needed packagesMiodrag Milanovic2018-09-193-1/+14
* | | Merge pull request #631 from acw1251/masterClifford Wolf2018-09-192-5/+5
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| * | Fixed typo in "verilog_write" help messageacw12512018-09-182-5/+5
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* | Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
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| * | Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
* | | Merge pull request #627 from acw1251/masterClifford Wolf2018-09-141-1/+1
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| * | | Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
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* | / Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
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* | Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
* | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
* | Add "make ystests"Clifford Wolf2018-08-303-0/+10
* | Add GCC to osx deps (#620)Miodrag Milanović2018-08-281-1/+1
* | Merge pull request #619 from mmicko/masterClifford Wolf2018-08-282-6/+0
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| * | Remove mercurial, since it is not needed anymoreMiodrag Milanovic2018-08-282-6/+0
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* | Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixesClifford Wolf2018-08-281-17/+112
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| * \ Merge branch 'master' into firrtl+modules+shiftfixesJim Lawson2018-08-2712-39/+92
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| | * \ Merge pull request #3 from YosysHQ/masterJim Lawson2018-08-2712-39/+92
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* | | | Add "make coverage"Clifford Wolf2018-08-278-13/+21
* | | | Add ENABLE_GCOV build optionClifford Wolf2018-08-271-0/+11
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