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* verilog: impose limit on maximum expression widthZachary Snow2021-03-043-0/+39
| | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* Update command-reference-manual.texClaire Xen2021-03-041-4/+4
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* Update READMEClaire Xen2021-03-041-4/+4
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* Merge pull request #2620 from zachjs/port-int-typeswhitequark2021-03-013-2/+64
|\ | | | | verilog: fix sizing of ports with int types in module headers
| * verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-013-2/+64
| | | | | | | | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* | Bump versionMarcelina Kościelnicka2021-03-011-1/+1
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* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-018-11/+197
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Set aside extraneous tests in simple_abc9 test suiteZachary Snow2021-03-012-0/+19
| | | | | | | New test cases on one branch may be automatically copied from simple/ to simple_abc9/, causing failures when switching to another branch. This updates the simple_abc9 script to set aside extraneous tests in a non-destructive way.
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
|\ | | | | Add -nosynthesis flag for read_verilog command
| * Fix indents.Tom Verbeure2021-01-041-2/+2
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| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
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* | Merge pull request #2524 from bkbncn/patch-1Claire Xen2021-03-011-0/+1
|\ \ | | | | | | Add boost-python3
| * | Add boost-python3Xiangyu Xu2021-01-041-0/+1
| |/ | | | | If enable python-api, do need boost-python3.
* | Merge pull request #2617 from RobertBaruch/docwhitequark2021-03-011-1/+1
|\ \ | | | | | | RTLIL Documentation: switch in process is optional
| * | RTLIL Documentation: switch in process is optionalRobert Baruch2021-02-271-1/+1
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* | | Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-017-12/+93
|\ \ \ | | | | | | | | genrtlil: improve name conflict error messaging
| * | | genrtlil: improve name conflict error messagingZachary Snow2021-02-267-12/+93
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* | | | Merge pull request #2618 from zachjs/int-typeswhitequark2021-02-286-39/+148
|\ \ \ \ | |_|/ / |/| | | sv: extended support for integer types
| * | | sv: extended support for integer typesZachary Snow2021-02-286-39/+148
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* | | Update issue_template.mdClaire Xen2021-02-271-1/+1
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* | | Add tests for $countbitsMichael Singer2021-02-262-0/+76
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* | | Implement $countones, $isunknown and $onehot{,0}Michael Singer2021-02-261-0/+28
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* | | Implement $countbits functionMichael Singer2021-02-261-0/+59
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* | | Extend simplify() recursion warningZachary Snow2021-02-261-1/+1
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* | | Bump versionMarcelina Kościelnicka2021-02-261-1/+1
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* | | Merge pull request #2554 from hzeller/masterwhitequark2021-02-251-6/+17
|\ \ \ | | | | | | | | Fix digit-formatting calculation for small numbers.
| * | | Provide an integer implementation of decimal_digits().Henner Zeller2021-02-011-2/+9
| | | | | | | | | | | | | | | | Signed-off-by: Henner Zeller <h.zeller@acm.org>
| * | | Fix digit-formatting calculation for small numbers.Henner Zeller2021-01-211-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling log10() on zero causes a non-sensical value to be calculated. On some compile options, I've observed yosys crashing with an illegal instruction (SIGILL). To make it safe, fix the calculation to do a range check; wrap it a decimal_digits() function, and use it where the previous ceil(log10(n)) call was used. As a side, it also improves readability. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* | | | btor, smt2, smv: Add a hint on how to deal with funny FF types.Marcelina Kościelnicka2021-02-253-3/+42
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* | | | Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-252-15/+16
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | Basically: - priority converts to (* full_case *) - unique0 converts to (* parallel_case *) - unique converts to (* parallel_case, full_case *) Fixes #2596.
* | | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-243-2/+445
| | | | | | | | | | | | turn-off (#2566)
* | | Merge pull request #2607 from zachjs/logger-error-atexitwhitequark2021-02-241-3/+3
|\ \ \ | | | | | | | | Fix double-free on unmatched logger error pattern
| * | | Fix double-free on unmatched logger error patternZachary Snow2021-02-231-3/+3
|/ / / | | | | | | | | | | | | | | | | | | When an expected logger error pattern is unmatched, the logger raises another (hidden) error. Because of the previous ordering of actions, `logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()` twice, causing a double-free.
* | | Add tests for some common techmap files.Marcelina Kościelnicka2021-02-243-0/+50
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* | | Fix syntax error in adff2dff.vMarcelina Kościelnicka2021-02-241-1/+1
| | | | | | | | | | | | Fixes #2600.
* | | frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-234-57/+71
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* | | Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-2310-47/+124
|\ \ \ | | | | | | | | verilog: fix sizing of constant args for tasks/functions
| * | | verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-2110-47/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | | | int -> boolRobert Baruch2021-02-231-2/+2
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* | | | Adds is_wire to SigBit and SigChunkRobert Baruch2021-02-231-0/+3
| | | | | | | | | | | | Useful for PYOSYS because Python can't easily check wire against NULL.
* | | | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵William D. Jones2021-02-232-12/+6
| | | | | | | | | | | | | | | | values.
* | | | machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
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* | | | machxo2: Add experimental status to help.William D. Jones2021-02-231-1/+1
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* | | | machxo2: Add DCCA and DCMA blackbox primitives.William D. Jones2021-02-231-0/+17
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* | | | machxo2: Fix reversed interpretation of REG_SD config bits.William D. Jones2021-02-231-2/+2
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* | | | machxo2: Tristate is active-low.William D. Jones2021-02-232-5/+5
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* | | | machxo2: Fix typos in FACADE_FF sim model.William D. Jones2021-02-231-5/+4
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* | | | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.William D. Jones2021-02-232-6/+6
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* | | | machxo2: Improve help_mode output in synth_machxo2.William D. Jones2021-02-231-5/+5
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* | | | machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires ↵William D. Jones2021-02-232-1/+17
| | | | | | | | | | | | | | | | to IO cells.
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