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| author | William D. Jones <thor0505@comcast.net> | 2021-02-21 09:14:37 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | ae07298a6b26315793167d9fe0e47d33412fc033 (patch) | |
| tree | 0b3450379e56b6c51fedfe2dcb23cc951967d19b | |
| parent | 353ace50345ab6a88f29dfe19c0ef813e7eb4e79 (diff) | |
| download | yosys-ae07298a6b26315793167d9fe0e47d33412fc033.tar.gz yosys-ae07298a6b26315793167d9fe0e47d33412fc033.tar.bz2 yosys-ae07298a6b26315793167d9fe0e47d33412fc033.zip | |
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 16 | ||||
| -rw-r--r-- | tests/arch/machxo2/mux.ys | 2 |
2 files changed, 6 insertions, 12 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index c6d70a055..161ddfe2e 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -4,17 +4,11 @@ module LUT4 #( input A, B, C, D, output Z ); - wire [3:0] I; - wire [3:0] I_pd; - - genvar ii; - generate - for (ii = 0; ii < 4; ii = ii + 1'b1) - assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii]; - endgenerate - - assign I = {D, C, B, A}; - assign Z = INIT[I_pd]; + // This form of LUT propagates as few x's as possible. + wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; + assign Z = A ? s1[1] : s1[0]; endmodule module FACADE_FF #( diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 0cfc365bd..6c8aa857c 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -35,6 +35,6 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:LUT4 +select -assert-count 11 t:LUT4 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D |