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| author | William D. Jones <thor0505@comcast.net> | 2021-01-31 23:57:13 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | e3974809ec55395fad4f6b407b03784f397e3f30 (patch) | |
| tree | 201e55742a3d51f5f6af665d73d6cf7c033ff128 | |
| parent | a1ea1430b6ba478267d30253a79936fcb9e5faef (diff) | |
| download | yosys-e3974809ec55395fad4f6b407b03784f397e3f30.tar.gz yosys-e3974809ec55395fad4f6b407b03784f397e3f30.tar.bz2 yosys-e3974809ec55395fad4f6b407b03784f397e3f30.zip | |
machxo2: Add DCCA and DCMA blackbox primitives.
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index e046d0c87..c6d70a055 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -188,6 +188,23 @@ module OSCH #( ); endmodule +(* blackbox *) +module DCCA ( + input CLKI, + input CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCMA ( + input CLK0, + input CLK1, + input SEL, + output DCMOUT +); +endmodule + // IO- "$__" cells for the iopadmap pass. These are temporary cells not meant // to be instantiated by the end user. They are required in this file for // attrmvcp to work. |