| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Support command files in Verific | Miodrag Milanovic | 2021-06-16 | 1 | -0/+39 |
| * | verilog: fix leaking of type names in parser | Xiretza | 2021-06-14 | 1 | -0/+2 |
| * | verilog: fix wildcard port connections leaking memory | Xiretza | 2021-06-14 | 1 | -0/+1 |
| * | ast: delete wires and localparams after finishing const evaluation | Xiretza | 2021-06-14 | 1 | -0/+8 |
| * | verilog: fix leaking ASTNodes | Xiretza | 2021-06-14 | 2 | -7/+15 |
| * | ast: fix error condition causing assert to fail | Xiretza | 2021-06-14 | 1 | -2/+1 |
| * | macos: fix leak in proc_self_dirname() | Zachary Snow | 2021-06-14 | 1 | -1/+3 |
| * | Simplify some RTLIL destructors | Rupert Swarbrick | 2021-06-14 | 1 | -10/+10 |
| * | verilog: Squash a memory leak. | Marcelina Kościelnicka | 2021-06-14 | 4 | -19/+14 |
| * | Add regression test for #2824. | Marcelina Kościelnicka | 2021-06-11 | 1 | -0/+7 |
| * | opt_muxtree: Update port_off and port_idx even for constant bits | gatecat | 2021-06-11 | 1 | -17/+16 |
| * | opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. | Marcelina Kościelnicka | 2021-06-09 | 3 | -122/+120 |
| * | opt_expr: Optimize div/mod by const 1. | Marcelina Kościelnicka | 2021-06-09 | 1 | -4/+4 |
| * | Merge pull request #2817 from YosysHQ/claire/fixemails | Claire Xen | 2021-06-09 | 325 | -1308/+1311 |
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| | * | Fix deadname SVN links | Claire Xenia Wolf | 2021-06-09 | 2 | -3/+3 |
| | * | Intersynth URL | Claire Xenia Wolf | 2021-06-09 | 2 | -2/+2 |
| | * | More deadname stuff | Claire Xenia Wolf | 2021-06-09 | 2 | -4/+4 |
| | * | Fix icestorm links | Claire Xenia Wolf | 2021-06-09 | 2 | -516/+516 |
| | * | More deadname stuff | Claire Xenia Wolf | 2021-06-09 | 10 | -27/+27 |
| | * | Use HTTPS for website links, gatecat email | Claire Xenia Wolf | 2021-06-09 | 20 | -26/+26 |
| | * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 5 | -422/+422 |
| | * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 309 | -331/+330 |
| | * | Add claire deadname stuff to .mailmap | Claire Xenia Wolf | 2021-06-08 | 1 | -0/+4 |
| * | | verilog: check for module scope identifiers during width detection | Zachary Snow | 2021-06-08 | 4 | -13/+41 |
| * | | mem2reg: tolerate out of bounds constant accesses | Zachary Snow | 2021-06-08 | 4 | -5/+94 |
| * | | autoname: simple perf optimizations | Zachary Snow | 2021-06-08 | 1 | -11/+15 |
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| * | sv: support tasks and functions within packages | Zachary Snow | 2021-06-01 | 5 | -2/+56 |
| * | kernel/mem: Recognize some deprecated memory port configs. | Marcelina Kościelnicka | 2021-06-01 | 1 | -0/+10 |
| * | memory_map: Improve start_offset handling. | Marcelina Kościelnicka | 2021-05-31 | 2 | -35/+131 |
| * | memory_share: Add read port merging. | Marcelina Kościelnicka | 2021-05-29 | 1 | -0/+140 |
| * | memory_share: Improve sat-based port sharing. | Marcelina Kościelnicka | 2021-05-28 | 1 | -117/+151 |
| * | Make a few passes auto-call Mem::narrow instead of rejecting wide ports. | Marcelina Kościelnicka | 2021-05-28 | 5 | -33/+10 |
| * | backends/verilog: Add support for memory read port reset and init value. | Marcelina Kościelnicka | 2021-05-27 | 1 | -9/+81 |
| * | backends/verilog: Add wide port support. | Marcelina Kościelnicka | 2021-05-27 | 1 | -43/+88 |
| * | memory_share: Improve same-address merging, recognize wide write ports. | Marcelina Kościelnicka | 2021-05-27 | 1 | -204/+77 |
| * | kernel/mem: Add helpers for write port widening. | Marcelina Kościelnicka | 2021-05-27 | 2 | -0/+57 |
| * | kernel/mem: Add sub_addr helpers. | Marcelina Kościelnicka | 2021-05-26 | 3 | -26/+32 |
| * | kernel/mem: Add prepare_wr_merge helper. | Marcelina Kościelnicka | 2021-05-26 | 2 | -0/+27 |
| * | backends/verilog: Try to preserve mem write port priorities. | Marcelina Kościelnicka | 2021-05-26 | 1 | -32/+84 |
| * | mem/extract_rdff: Fix "no FF made" edge case. | Marcelina Kościelnicka | 2021-05-25 | 2 | -3/+9 |
| * | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 5 | -40/+52 |
| * | verilog: fix case expression sign and width handling | Zachary Snow | 2021-05-25 | 5 | -12/+157 |
| * | sv: support remaining assignment operators | Zachary Snow | 2021-05-25 | 3 | -42/+64 |
| * | mem/extract_rdff: Add alternate transparency handling. | Marcelina Kościelnicka | 2021-05-25 | 1 | -18/+80 |
| * | opt_mem: Add reset/init value support. | Marcelina Kościelnicka | 2021-05-25 | 1 | -0/+12 |
| * | kernel/mem: Add model support for read port init value and resets. | Marcelina Kościelnicka | 2021-05-25 | 2 | -4/+73 |
| * | mem/extract_rdff: Fix wire naming and wide port support. | Marcelina Kościelnicka | 2021-05-25 | 1 | -6/+22 |
| * | memory_bram: Respect write port priority. | Marcelina Kościelnicka | 2021-05-25 | 1 | -0/+14 |
| * | opt_mem_feedback: Respect write port priority. | Marcelina Kościelnicka | 2021-05-25 | 2 | -0/+62 |
| * | kernel/mem: Add emulate_priority helper. | Marcelina Kościelnicka | 2021-05-25 | 2 | -0/+44 |
