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| * | | | | | | | | | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| * | | | | | | | | | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| * | | | | | | | | | Add defaultvalue attributeClifford Wolf2019-06-192-0/+15
| * | | | | | | | | | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
* | | | | | | | | | | Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
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* | | | | | | | | | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-195-0/+8
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| * | | | | | | | | | Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| * | | | | | | | | | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
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* | | | | | | | | | Merge pull request #1104 from whitequark/case-semanticsClifford Wolf2019-06-192-1/+40
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| * | | | | | | | | Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
| * | | | | | | | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | | | | | | | | Merge pull request #1086 from udif/pr_elab_sys_tasks2Clifford Wolf2019-06-182-3/+13
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| * | | | | | | | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
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* | | | | | | / Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
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* | | | | | | Merge pull request #829 from abdelrahmanhosny/masterSerge Bazanski2019-06-132-0/+46
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| * | | | | | address review commentsAbdelrahman2019-03-011-23/+9
| * | | | | | add dockerignore fileAbdelrahman2019-02-261-0/+13
| * | | | | | dockerize yosysAbdelrahman2019-02-261-0/+47
* | | | | | | Add some more commentsEddie Hung2019-06-101-1/+6
* | | | | | | Merge pull request #1082 from corecode/u4kDavid Shah2019-06-101-0/+24
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| * | | | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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* | | | | | | Merge pull request #1078 from YosysHQ/eddie/muxcover_costsClifford Wolf2019-06-081-12/+42
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| * | | | | | Allow muxcover costs to be changedEddie Hung2019-06-071-12/+42
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* | | | | | Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
* | | | | | Merge pull request #1079 from YosysHQ/eddie/fix_read_aigerClifford Wolf2019-06-0727-45/+128
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| * | | | | | Add read_aiger to CHANGELOGEddie Hung2019-06-071-0/+1
| * | | | | | Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
| * | | | | | Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
| * | | | | | Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| * | | | | | Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
| * | | | | | Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| * | | | | | Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| * | | | | | Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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* | | | | | Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-079-3/+93
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| * | | | | | Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-074-50/+38
| * | | | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-0710-5/+107
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| | * | | | | | Initial implementation of elaboration system tasksUdi Finkelstein2019-05-0310-5/+107
* | | | | | | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
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* | | | | | | Merge branch 'tux3-implicit_named_connection'Clifford Wolf2019-06-074-3/+40
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| * | | | | | | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-073-13/+2
| * | | | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-075-4/+52
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| | * | | | | | SystemVerilog support for implicit named port connectionstux32019-06-065-12/+59
* | | | | | | | Merge pull request #1076 from thasti/centos7-build-fixClifford Wolf2019-06-071-1/+0
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| * | | | | | | remove boost/log/exceptions.hpp from wrapper generatorStefan Biereigel2019-06-071-1/+0
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* | | | | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-0614-10/+279
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| * | | | | | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| * | | | | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...Maciej Kurc2019-06-044-0/+46
| * | | | | | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
| * | | | | | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
* | | | | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
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