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* abc9_ops: move assertEddie Hung2020-05-141-1/+1
* abc9: put 'aigmap' backEddie Hung2020-05-141-0/+1
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
* abc9_ops: fix bypass boxes using (* abc9_bypass *)Eddie Hung2020-05-142-14/+10
* abc9_ops: tidy up, suppress error if no boxes/holesEddie Hung2020-05-141-18/+18
* abc9_ops: -prep_delays to not insert delay box if input connection is constEddie Hung2020-05-141-0/+2
* abc9_ops: cleanup; -prep_dff -> -prep_dff_submodEddie Hung2020-05-142-22/+14
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-1411-941/+667
* abc9_ops: -reintegrate to handle $_FF_; cleanupEddie Hung2020-05-141-22/+18
* xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarityEddie Hung2020-05-141-16/+5
* aiger: -xaiger to return $_FF_ flopsEddie Hung2020-05-141-15/+2
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-144-12/+48
* abc9: test to use box file instead of autoEddie Hung2020-05-143-2/+5
* abc9: restore selected_modules()Eddie Hung2020-05-141-1/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
* Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"Eddie Hung2020-05-141-4/+0
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-147-24/+88
* kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zeroEddie Hung2020-05-141-10/+6
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-142-9/+7
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* abc9: remove redundant wbflipEddie Hung2020-05-141-1/+0
* xaiger: always sort input/output bits by port idEddie Hung2020-05-141-12/+10
* abc9: generate $abc9_holes design instead of <name>$holesEddie Hung2020-05-143-18/+28
* abc9_ops: more robustEddie Hung2020-05-141-8/+14
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-143-38/+66
* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
* aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-142-10/+13
* abc9: cleanupEddie Hung2020-05-141-7/+11
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
* abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module outputEddie Hung2020-05-141-1/+5
* abc9_ops: do away with '$abc9_cells' selectionEddie Hung2020-05-142-40/+30
* abc9_ops: use new 'design -delete' and 'select -unset'Eddie Hung2020-05-142-16/+7
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* submod: revert accidental changeEddie Hung2020-05-141-1/+1
* Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"Eddie Hung2020-05-141-1/+0
* xaiger: update help textEddie Hung2020-05-141-4/+4
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
* abc9_ops: -prep_dff_map to warn if no specify cellsEddie Hung2020-05-141-7/+12
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
* kernel: Module::makeblackbox() to clear connections + delete wires lastEddie Hung2020-05-141-0/+1
* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
* abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flopsEddie Hung2020-05-141-12/+39
* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
* xaiger: do not treat (* init=1'bx *) as 1'b0Eddie Hung2020-05-141-1/+1
* abc9: cleanupEddie Hung2020-05-141-4/+1
* abc9_ops: do not use (* abc9_init *)Eddie Hung2020-05-141-16/+31
* aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
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