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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-14 10:36:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | a52f779ecae79be5ea79bd27f04837e7031f8415 (patch) | |
| tree | e0ea9fbc1631f6c507ce73939cab0775c6feaf86 | |
| parent | 509de98468973838aa3b3ff958084693434c8c83 (diff) | |
| download | yosys-a52f779ecae79be5ea79bd27f04837e7031f8415.tar.gz yosys-a52f779ecae79be5ea79bd27f04837e7031f8415.tar.bz2 yosys-a52f779ecae79be5ea79bd27f04837e7031f8415.zip | |
ecp5: (* abc9_flop *) gated behind YOSYS
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 69685683f..563592218 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -294,7 +294,9 @@ endmodule // --------------------------------------- +`ifdef YOSYS (* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *) +`endif module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); parameter GSR = "ENABLED"; parameter [127:0] CEMUX = "1"; |