| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Progress in new BTOR back-end | Clifford Wolf | 2017-11-23 | 1 | -3/+95 |
| | | |||||
| * | Progress in new BTOR back-end | Clifford Wolf | 2017-11-23 | 1 | -14/+72 |
| | | |||||
| * | Merge branch 'master' into btor-ng | Clifford Wolf | 2017-11-23 | 3 | -13/+121 |
| |\ | |||||
| | * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-11-23 | 1 | -0/+103 |
| | |\ | |||||
| | | * | Merge pull request #455 from daveshah1/up5k | Clifford Wolf | 2017-11-18 | 1 | -0/+103 |
| | | |\ | | | | | | | | | Add UltraPlus specific cells to ice40 techlib | ||||
| | | | * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
| | | | | | |||||
| | | | * | Merge branch 'master' into up5k | David Shah | 2017-11-17 | 2 | -5/+29 |
| | | | |\ | |||||
| | | | * | | Add some UltraPlus cells to ice40 techlib | David Shah | 2017-11-16 | 1 | -0/+103 |
| | | | | | | |||||
| | * | | | | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 2 | -13/+18 |
| | |/ / / | |||||
| * | | | | Progress with new BTOR backend | Clifford Wolf | 2017-11-23 | 1 | -8/+109 |
| | | | | | |||||
| * | | | | Add skeleton for new BTOR back-end | Clifford Wolf | 2017-11-23 | 2 | -0/+216 |
| | | | | | |||||
| * | | | | Remove old BTOR back-end | Clifford Wolf | 2017-11-23 | 4 | -1174/+0 |
| |/ / / | |||||
| * | | | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 |
| | | | | |||||
| * | | | Merge pull request #452 from cr1901/master | Clifford Wolf | 2017-11-18 | 1 | -4/+20 |
| |\ \ \ | | | | | | | | | Accommodate Windows-style paths during include-file processing. | ||||
| | * | | | Accommodate Windows-style paths during include-file processing. | William D. Jones | 2017-11-14 | 1 | -4/+20 |
| | |/ / | |||||
| * | | | Merge pull request #453 from dh73/master | Clifford Wolf | 2017-11-18 | 14 | -9/+316 |
| |\ \ \ | |_|/ |/| | | Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells | ||||
| | * | | Fixed the -vout flag to -vqm in examples/intel directory | dh73 | 2017-11-14 | 4 | -4/+4 |
| | | | | |||||
| | * | | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
| | | | | |||||
| | * | | Merge https://github.com/cliffordwolf/yosys | dh73 | 2017-11-08 | 25 | -449/+588 |
| | |\| | |||||
| | * | | Organizing Speedster file names | dh73 | 2017-11-08 | 5 | -4/+4 |
| | | | | |||||
| * | | | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
| | |/ |/| | |||||
| * | | Add support for editline as replacement for readline | Clifford Wolf | 2017-11-08 | 4 | -10/+39 |
| | | | |||||
| * | | Add "ltp" command | Clifford Wolf | 2017-10-31 | 2 | -0/+186 |
| | | | |||||
| * | | Fix SMT2 handling of initstate in sub-modules | Clifford Wolf | 2017-10-29 | 1 | -0/+3 |
| | | | |||||
| * | | Fix memory corruption bug in opt_rmdff | Clifford Wolf | 2017-10-26 | 1 | -0/+3 |
| | | | |||||
| * | | Fix typo in opt_clean log message | Clifford Wolf | 2017-10-26 | 1 | -1/+1 |
| | | | |||||
| * | | Improve smtio performance by using reader thread, not writer thread | Clifford Wolf | 2017-10-26 | 1 | -10/+30 |
| | | | |||||
| * | | Use separate writer thread for talking to SMT solver to avoid read/write ↵ | Clifford Wolf | 2017-10-25 | 1 | -8/+23 |
| | | | | | | | | | deadlock | ||||
| * | | Improve p_* functions in smtio.py | Clifford Wolf | 2017-10-25 | 1 | -21/+19 |
| | | | |||||
| * | | Disable OSX in .travis.yml | Clifford Wolf | 2017-10-25 | 1 | -2/+2 |
| | | | |||||
| * | | Add ENABLE_DEBUG config flag | Clifford Wolf | 2017-10-25 | 1 | -1/+10 |
| | | | |||||
| * | | Update ABC to hg rev f6838749f234 | Clifford Wolf | 2017-10-25 | 1 | -1/+1 |
| | | | |||||
| * | | Remove vhdl2verilog | Clifford Wolf | 2017-10-25 | 2 | -184/+0 |
| | | | |||||
| * | | Capsulate smt-solver read/write in separate functions | Clifford Wolf | 2017-10-25 | 1 | -8/+24 |
| | | | |||||
| * | | Fix a bug in yosys-smtbmc in ROM handling | Clifford Wolf | 2017-10-25 | 1 | -0/+3 |
| | | | |||||
| * | | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 2 | -35/+1 |
| | | | |||||
| * | | Remove all PSL support code from verific.cc | Clifford Wolf | 2017-10-20 | 1 | -179/+17 |
| | | | |||||
| * | | Merge pull request #437 from mithro/master | Clifford Wolf | 2017-10-20 | 2 | -1/+14 |
| |\ \ | | | | | | | Adding COPYING file with license information. | ||||
| | * | | Adding COPYING file with license information. | Tim 'mithro' Ansell | 2017-10-19 | 2 | -1/+14 |
| |/ / | | | | | | | | | This allows GitHub and other tools to detect the license info. Providing a COPYING for LICENSE file is also pretty standard. | ||||
| * | | Revert 90be0d8 as it causes endless loops for some designs | Clifford Wolf | 2017-10-14 | 1 | -1/+0 |
| | | | |||||
| * | | Add "verific -vlog-libdir" | Clifford Wolf | 2017-10-13 | 1 | -0/+12 |
| | | | |||||
| * | | Add "verific -vlog-incdir" and "verific -vlog-define" | Clifford Wolf | 2017-10-13 | 1 | -0/+35 |
| | | | |||||
| * | | Update Verific README | Clifford Wolf | 2017-10-13 | 1 | -0/+7 |
| | | | |||||
| * | | Merge pull request #434 from Kmanfi/vector_fix | Clifford Wolf | 2017-10-12 | 1 | -0/+1 |
| |\ \ | | | | | | | Fix input vector for reduce cells. | ||||
| | * | | Fix input vector for reduce cells. | Kaj Tuomi | 2017-10-12 | 1 | -0/+1 |
| | | | | |||||
| * | | | Add Verific fairness/liveness support | Clifford Wolf | 2017-10-12 | 1 | -11/+32 |
| |/ / | |||||
| * | | Update ABC to hg rev 6283c5d99b06 | Clifford Wolf | 2017-10-11 | 1 | -1/+1 |
| | | | |||||
| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-10-10 | 28 | -211/+234 |
| |\ \ | |||||
| | * | | Rewrite ABC output to include proper net names in timing report | Clifford Wolf | 2017-10-10 | 1 | -2/+17 |
| | | | | |||||
| | * | | Add timing constraints to osu035 example | Clifford Wolf | 2017-10-10 | 3 | -2/+4 |
| | | | | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |