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authorClifford Wolf <clifford@clifford.at>2017-11-23 08:57:55 +0100
committerClifford Wolf <clifford@clifford.at>2017-11-23 08:57:55 +0100
commit494a6f79492d871adae7af10d3d173454b3ecb21 (patch)
treee994cad360987980197ee1e9f95b4e8cf5542e22
parent777f2881d880c7690c33821a90c990a8cebd275d (diff)
parent4782d59a3f15eeac5251f5f99ceadd89c9a30c93 (diff)
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Merge branch 'master' of github.com:cliffordwolf/yosys
-rw-r--r--techlibs/ice40/cells_sim.v103
1 files changed, 103 insertions, 0 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 7778b5519..2bcab8884 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,3 +881,106 @@ module SB_WARMBOOT (
input S0
);
endmodule
+
+// UltraPlus feature cells
+(* blackbox *)
+module SB_MAC16 (
+ input CLK,
+ input CE,
+ input [15:0] C,
+ input [15:0] A,
+ input [15:0] B,
+ input [15:0] D,
+ input AHOLD,
+ input BHOLD,
+ input CHOLD,
+ input DHOLD,
+ input IRSTTOP,
+ input IRSTBOT,
+ input ORSTTOP,
+ input ORSTBOT,
+ input OLOADTOP,
+ input OLOADBOT,
+ input ADDSUBTOP,
+ input ADDSUBBOT,
+ input OHOLDTOP,
+ input OHOLDBOT,
+ input CI,
+ input ACCUMCI,
+ input SIGNEXTIN,
+ output [31:0] O,
+ output CO,
+ output ACCUMCO,
+ output SIGNEXTOUT
+);
+parameter NEG_TRIGGER = 1'b0;
+parameter C_REG = 1'b0;
+parameter A_REG = 1'b0;
+parameter B_REG = 1'b0;
+parameter D_REG = 1'b0;
+parameter TOP_8x8_MULT_REG = 1'b0;
+parameter BOT_8x8_MULT_REG = 1'b0;
+parameter PIPELINE_16x16_MULT_REG1 = 1'b0;
+parameter PIPELINE_16x16_MULT_REG2 = 1'b0;
+parameter TOPOUTPUT_SELECT = 2'b00;
+parameter TOPADDSUB_LOWERINPUT = 2'b00;
+parameter TOPADDSUB_UPPERINPUT = 1'b0;
+parameter TOPADDSUB_CARRYSELECT = 2'b00;
+parameter BOTOUTPUT_SELECT = 2'b00;
+parameter BOTADDSUB_LOWERINPUT = 2'b00;
+parameter BOTADDSUB_UPPERINPUT = 1'b0;
+parameter BOTADDSUB_CARRYSELECT = 2'b00;
+parameter MODE_8x8 = 1'b0;
+parameter A_SIGNED = 1'b0;
+parameter B_SIGNED = 1'b0;
+endmodule
+
+(* blackbox *)
+module SB_SPRAM256KA(
+ input [13:0] ADDRESS,
+ input [15:0] DATAIN,
+ input [3:0] MASKWREN,
+ input WREN,
+ input CHIPSELECT,
+ input CLOCK,
+ input STANDBY,
+ input SLEEP,
+ input POWEROFF,
+ output [15:0] DATAOUT
+);
+endmodule
+
+(* blackbox *)
+module SB_HFOSC(
+ input CLKHFPU,
+ input CLKHFEN,
+ output CLKHF
+);
+parameter CLKHF_DIV = "0b00";
+endmodule
+
+(* blackbox *)
+module SB_LFOSC(
+ input CLKLFPU,
+ input CLKLFEN,
+ output CLKLF
+);
+endmodule
+
+(* blackbox *)
+module SB_RGBA_DRV(
+ input CURREN,
+ input RGBLEDEN,
+ input RGB0PWM,
+ input RGB1PWM,
+ input RGB2PWM,
+ output RGB0,
+ output RGB1,
+ output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+