iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-01-05	5	-42/+135
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\| *	Fixed handling of local memories in functions	Clifford Wolf	2017-01-05	1	-2/+2
\| *	Added "check -initdrv"	Clifford Wolf	2017-01-04	1	-3/+82
\| *	Added handling of local memories and error for local decls in unnamed blocks	Clifford Wolf	2017-01-04	1	-1/+10
\| *	Implicitly set "yosys-smtbmc --noprogress" on windows	Clifford Wolf	2017-01-04	1	-3/+4
\| *	Fixed typo in tests/simple/arraycells.v	Clifford Wolf	2017-01-04	1	-1/+1
\| *	Fixed "yosys-smtbmc --noprogress"	Clifford Wolf	2017-01-04	1	-1/+1
\| *	Added Verilog $rtoi and $itor support	Clifford Wolf	2017-01-03	1	-24/+30
\| *	Handle "always 1" like "always -1" in .smtc files	Clifford Wolf	2017-01-02	1	-7/+5
* \|	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-01-01	4	-4/+65
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\| *	Added cell port resizing to hierarchy pass	Clifford Wolf	2017-01-01	1	-0/+56
\| *	Updated ABC to hg id 55cd83f432c0	Clifford Wolf	2016-12-31	1	-1/+1
\| *	Bugfix in RTLIL::SigSpec::remove2()	Clifford Wolf	2016-12-31	1	-3/+4
\| *	Updated ABC to hg id 8c6a635f7a20	Clifford Wolf	2016-12-29	1	-1/+1
\| *	Improved write_json help message	Clifford Wolf	2016-12-29	1	-0/+4
\| *	Updated ABC to hg id f591c081d5e7	Clifford Wolf	2016-12-26	1	-1/+1
\| *	Merge pull request #284 from azonenberg/master	Clifford Wolf	2016-12-24	6	-65/+328
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* \| \|	greenpak4: Added POUT to GP_COUNTx cells	Andrew Zonenberg	2017-01-01	1	-3/+4
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* \|	Merge pull request #1 from azonenberg-hk/master	Andrew Zonenberg	2016-12-23	19	-70/+586
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\| * \|	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-12-23	5	-4/+44
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\| \| *	Simplified log_spacer() code	Clifford Wolf	2016-12-23	1	-6/+2
\| \| *	Added "yosys -W regex"	Clifford Wolf	2016-12-22	3	-2/+44
\| \| *	Added AIGER back-end to automatic back-end detection	Clifford Wolf	2016-12-21	1	-0/+2
\| \| *	Updated ABC to hg rev a4872e22c646	Clifford Wolf	2016-12-21	1	-1/+1
\| \| *	Updated ABC to hg rev 8bab2eedbba4	Clifford Wolf	2016-12-21	1	-1/+1
\| * \|	greenpak4: Added INT pin to GP_SPI	Andrew Zonenberg	2016-12-21	1	-1/+3
\| * \|	greenpak4: removed unused MISO pin from GP_SPI	Andrew Zonenberg	2016-12-21	1	-1/+0
\| * \|	greenpak4: Removed SPI_BUFFER parameter	Andrew Zonenberg	2016-12-20	1	-1/+0
\| * \|	greenpak4: replaced MOSI/MISO with single one-way SDAT pin	Andrew Zonenberg	2016-12-20	1	-2/+1
\| * \|	greenpak4: Changed port names on GP_SPI for clarity	Andrew Zonenberg	2016-12-20	1	-4/+4
\| * \|	greenpak4: Initial implementation of GP_SPI cell	Andrew Zonenberg	2016-12-20	1	-0/+27
\| * \|	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-12-17	2	-1/+61
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\| \| *	Added "verilog_defines" command	Clifford Wolf	2016-12-15	1	-0/+60
\| \| *	Bugfix in comment handling	Clifford Wolf	2016-12-13	1	-1/+1
\| * \|	greenpak4: Updated GP_DCMP cell model	Andrew Zonenberg	2016-12-17	1	-2/+20
\| * \|	greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.	Andrew Zonenberg	2016-12-16	1	-5/+10
\| * \|	greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed inte...	Andrew Zonenberg	2016-12-15	1	-5/+24
\| * \|	greenpak4: More fixups of GP_DCMPx cells	Andrew Zonenberg	2016-12-15	1	-9/+3
\| * \|	greenpak4: And another typo :(	Andrew Zonenberg	2016-12-15	1	-1/+1
\| * \|	greenpak4: Fixed another typo	Andrew Zonenberg	2016-12-15	1	-1/+1
\| * \|	greenpak4: Fixed typo	Andrew Zonenberg	2016-12-15	1	-1/+1
\| * \|	greenpak4: Cleaned up trailing spaces in cells_sim	Andrew Zonenberg	2016-12-14	1	-60/+60
\| * \|	greenpak4: Added GP_DCMPREF / GP_DCMPMUX	Andrew Zonenberg	2016-12-14	1	-0/+23
\| * \|	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-12-12	7	-0/+153
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\| \| *	Added $anyconst support to AIGER back-end	Clifford Wolf	2016-12-11	1	-0/+7
\| \| *	Merge branch 'LSS-USP-unit-test-structure'	Clifford Wolf	2016-12-11	6	-0/+146
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\| \| *	Some minor CodingReadme changes in unit test section	Clifford Wolf	2016-12-11	1	-10/+4
\| \| *	Build hotfix in tests/unit/Makefile	Clifford Wolf	2016-12-11	1	-1/+1
\| \| *	Improved unit test structure	rodrigosiqueira	2016-12-10	3	-16/+20
\| \| *	Added explanation about configure and create test	rodrigosiqueira	2016-12-04	1	-0/+75