Merge pull request #1 from azonenberg-hk/master

Pull changes from HK trip

19 files changed, 586 insertions, 70 deletions

diff --git a/.gitignore b/.gitignore
index 93e28cd6c..cd624f233 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,7 @@
 *.o
 *.d
 .*.swp
+*.gch
 /.cproject
 /.project
 /.settings
@@ -27,3 +28,5 @@
 /yosys-win32-vcxsrc-*
 /yosysjs-*
 /libyosys.so
+/tests/unit/bintest/
+/tests/unit/objtest/
diff --git a/CodingReadme b/CodingReadme
index cbe1fb8be..9e85add28 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -411,3 +411,72 @@ Updating the website:
 	git commit -am update
 	make push
 
+How to add unit test
+====================
+
+Unit test brings some advantages, briefly, we can list some of them (reference
+[1](https://en.wikipedia.org/wiki/Unit_testing)):
+
+* Tests reduce bugs in new features;
+* Tests reduce bugs in existing features;
+* Tests are good documentation;
+* Tests reduce the cost of change;
+* Tests allow refactoring;
+
+With those advantages in mind, it was required to choose a framework which fits
+well with C/C++ code.  Hence, it was chosen (google test)
+[https://github.com/google/googletest], because it is largely used and it is
+relatively easy learn.
+
+Install and configure google test (manually)
+--------------------------------------------
+
+In this section, you will see a brief description of how to install google
+test. However, it is strongly recommended that you take a look to the official
+repository (https://github.com/google/googletest) and refers to that if you
+have any problem to install it. Follow the steps below:
+
+* Install: cmake and pthread
+* Clone google test project from: https://github.com/google/googletest and
+  enter in the project directory
+* Inside project directory, type:
+
+```
+cmake -DBUILD_SHARED_LIBS=ON .
+make
+```
+
+* After compilation, copy all "*.so" inside directory "googlemock" and
+  "googlemock/gtest" to "/usr/lib/"
+* Done! Now you can compile your tests.
+
+If you have any problem, go to the official repository to find help.
+
+Ps.: Some distros already have googletest packed. If your distro supports it,
+you can use it instead of compile.
+
+Create new unit test
+--------------------
+
+If you want to add new unit tests for Yosys, just follow the steps below:
+
+* Go to directory "yosys/test/unit/"
+* In this directory you can find something similar Yosys's directory structure.
+  To create your unit test file you have to follow this pattern:
+  fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the
+  unit test for kernel/celledges.cc, you will need to create a file like this:
+  tests/unit/kernel/celledgesTest.cc;
+* Implement your unit test
+
+Run unit test
+-------------
+
+To compile and run all unit tests, just go to yosys root directory and type:
+```
+make unit-test
+```
+
+If you want to remove all unit test files, type:
+```
+make clean-unit-test
+```
diff --git a/Makefile b/Makefile
index 9bf67d349..ea2395ee9 100644
--- a/Makefile
+++ b/Makefile
@@ -45,6 +45,9 @@ TARGETS = yosys$(EXE) yosys-config
 PRETTY = 1
 SMALL = 0
 
+# Unit test
+UNITESTPATH := tests/unit
+
 all: top-all
 
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
@@ -83,7 +86,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 8b555d9e67cf
+ABCREV = a4872e22c646
 ABCPULL = 1
 ABCURL ?= https://bitbucket.org/alanmi/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"
@@ -447,6 +450,14 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Passed \"make vloghtb\"."
 	@echo ""
 
+# Unit test
+unit-test: libyosys.so
+	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
+		CXXFLAGS="$(CXXFLAGS)" LDLIBS="$(LDLIBS)" ROOTPATH="$(CURDIR)"
+
+clean-unit-test:
+	@$(MAKE) -C $(UNITESTPATH) clean
+
 install: $(TARGETS) $(EXTRA_TARGETS)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR)
 	$(INSTALL_SUDO) install $(TARGETS) $(DESTDIR)$(BINDIR)
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index aefe5cf43..ab1fba6f1 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -163,6 +163,13 @@ struct AigerWriter
 				continue;
 			}
 
+			if (cell->type == "$anyconst")
+			{
+				for (auto bit : sigmap(cell->getPort("\\Y")))
+					ff_map[bit] = bit;
+				continue;
+			}
+
 			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
 
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 2a1dce389..fe84c8e80 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -436,6 +436,66 @@ struct VerilogDefaults : public Pass {
 	}
 } VerilogDefaults;
 
+struct VerilogDefines : public Pass {
+	VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    verilog_defines [options]\n");
+		log("\n");
+		log("Define and undefine verilog preprocessor macros.\n");
+		log("\n");
+		log("    -Dname[=definition]\n");
+		log("        define the preprocessor symbol 'name' and set its optional value\n");
+		log("        'definition'\n");
+		log("\n");
+		log("    -Uname[=definition]\n");
+		log("        undefine the preprocessor symbol 'name'\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-D" && argidx+1 < args.size()) {
+				std::string name = args[++argidx], value;
+				size_t equal = name.find('=');
+				if (equal != std::string::npos) {
+					value = name.substr(equal+1);
+					name = name.substr(0, equal);
+				}
+				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				continue;
+			}
+			if (arg.compare(0, 2, "-D") == 0) {
+				size_t equal = arg.find('=', 2);
+				std::string name = arg.substr(2, equal-2);
+				std::string value;
+				if (equal != std::string::npos)
+					value = arg.substr(equal+1);
+				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				continue;
+			}
+			if (arg == "-U" && argidx+1 < args.size()) {
+				std::string name = args[++argidx];
+				design->verilog_defines.erase(name);
+				continue;
+			}
+			if (arg.compare(0, 2, "-U") == 0) {
+				std::string name = arg.substr(2);
+				design->verilog_defines.erase(name);
+				continue;
+			}
+			break;
+		}
+
+		if (args.size() != argidx)
+			cmd_error(args, argidx, "Extra argument.");
+	}
+} VerilogDefines;
+
 YOSYS_NAMESPACE_END
 
 // the yyerror function used by bison to report parser errors
diff --git a/kernel/driver.cc b/kernel/driver.cc
index f8d00c38d..3652ff4f1 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -218,6 +218,9 @@ int main(int argc, char **argv)
 		printf("        yosys_dump_<header_id>.il is used as filename if none is specified.\n");
 		printf("        Use 'ALL' as <header_id> to dump at every header.\n");
 		printf("\n");
+		printf("    -W regex\n");
+		printf("        print a warning for all log messages matching the regex \n");
+		printf("\n");
 		printf("    -V\n");
 		printf("        print version information and exit\n");
 		printf("\n");
@@ -238,7 +241,7 @@ int main(int argc, char **argv)
 	}
 
 	int opt;
-	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:D:")) != -1)
+	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:D:")) != -1)
 	{
 		switch (opt)
 		{
@@ -320,6 +323,12 @@ int main(int argc, char **argv)
 			scriptfile = optarg;
 			scriptfile_tcl = true;
 			break;
+		case 'W':
+			log_warn_regexes.push_back(std::regex(optarg,
+					std::regex_constants::nosubs |
+					std::regex_constants::optimize |
+					std::regex_constants::egrep));
+			break;
 		case 'D':
 			{
 				auto args = split_tokens(optarg, ":");
diff --git a/kernel/log.cc b/kernel/log.cc
index abc401f55..cd16bb344 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -41,6 +41,7 @@ YOSYS_NAMESPACE_BEGIN
 std::vector<FILE*> log_files;
 std::vector<std::ostream*> log_streams;
 std::map<std::string, std::set<std::string>> log_hdump;
+std::vector<std::regex> log_warn_regexes;
 bool log_hdump_all = false;
 FILE *log_errfile = NULL;
 SHA1 *log_hasher = NULL;
@@ -136,6 +137,32 @@ void logv(const char *format, va_list ap)
 
 	for (auto f : log_streams)
 		*f << str;
+
+	static std::string linebuffer;
+	static bool log_warn_regex_recusion_guard = false;
+
+	if (!log_warn_regex_recusion_guard)
+	{
+		log_warn_regex_recusion_guard = true;
+
+		if (log_warn_regexes.empty())
+		{
+			linebuffer.clear();
+		}
+		else
+		{
+			linebuffer += str;
+
+			if (!linebuffer.empty() && linebuffer.back() == '\n') {
+				for (auto &re : log_warn_regexes)
+					if (std::regex_search(linebuffer, re))
+						log_warning("Found log message matching -W regex:\n%s", str.c_str());
+				linebuffer.clear();
+			}
+		}
+
+		log_warn_regex_recusion_guard = false;
+	}
 }
 
 void logv_header(RTLIL::Design *design, const char *format, va_list ap)
@@ -262,8 +289,8 @@ void log_cmd_error(const char *format, ...)
 
 void log_spacer()
 {
-	while (log_newline_count < 2)
-		log("\n");
+	if (log_newline_count < 2) log("\n");
+	if (log_newline_count < 2) log("\n");
 }
 
 void log_push()
diff --git a/kernel/log.h b/kernel/log.h
index 53480db31..5b1729eb1 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -23,6 +23,7 @@
 #define LOG_H
 
 #include <time.h>
+#include <regex>
 
 #ifndef _WIN32
 #  include <sys/time.h>
@@ -48,6 +49,7 @@ struct log_cmd_error_exception { };
 extern std::vector<FILE*> log_files;
 extern std::vector<std::ostream*> log_streams;
 extern std::map<std::string, std::set<std::string>> log_hdump;
+extern std::vector<std::regex> log_warn_regexes;
 extern bool log_hdump_all;
 extern FILE *log_errfile;
 extern SHA1 *log_hasher;
diff --git a/kernel/register.cc b/kernel/register.cc
index 7a1d0b44b..983577682 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -173,7 +173,7 @@ void Pass::call(RTLIL::Design *design, std::string command)
 	}
 
 	while (!tok.empty()) {
-		if (tok == "#") {
+		if (tok[0] == '#') {
 			int stop;
 			for (stop = 0; stop < GetSize(cmd_buf); stop++)
 				if (cmd_buf[stop] == '\r' || cmd_buf[stop] == '\n')
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 08fee9741..3d0aca78e 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
 			command = "verilog";
 		else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
 			command = "ilang";
+		else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
+			command = "aiger";
 		else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
 			command = "blif";
 		else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")
diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 1c9871e2f..7482af6c6 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/greenpak4/synth_greenpak4.o
 OBJS += techlibs/greenpak4/greenpak4_counters.o
 OBJS += techlibs/greenpak4/greenpak4_dffinv.o
 
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
 $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
diff --git a/techlibs/greenpak4/cells_latch.v b/techlibs/greenpak4/cells_latch.v
new file mode 100644
index 000000000..2ccdd2031
--- /dev/null
+++ b/techlibs/greenpak4/cells_latch.v
@@ -0,0 +1,15 @@
+module $_DLATCH_P_(input E, input D, output Q);
+	GP_DLATCH _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(!E),
+		.Q(Q)
+		);
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+	GP_DLATCH _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(E),
+		.Q(Q)
+		);
+endmodule
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 111a77a14..f8fb2569a 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 	);
 endmodule
 
+module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSR #(
+		.INIT(INIT),
+		.SRMODE(1'b1),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nSET),
+		.Q(Q)
+	);
+endmodule
+
+module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSR #(
+		.INIT(INIT),
+		.SRMODE(1'b0),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nRST),
+		.Q(Q)
+	);
+endmodule
+
+module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSRI #(
+		.INIT(INIT),
+		.SRMODE(1'b1),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nSET),
+		.nQ(nQ)
+	);
+endmodule
+
+module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	GP_DLATCHSRI #(
+		.INIT(INIT),
+		.SRMODE(1'b0),
+	) _TECHMAP_REPLACE_ (
+		.D(D),
+		.nCLK(nCLK),
+		.nSR(nRST),
+		.nQ(nQ)
+	);
+endmodule
+
 module GP_OBUFT(input IN, input OE, output OUT);
 	GP_IOBUF _TECHMAP_REPLACE_ (
 		.IN(IN),
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 80746be0f..dd21bdd50 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -16,11 +16,15 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 endmodule
 
 module GP_ABUF(input wire IN, output wire OUT);
-	
+
 	assign OUT = IN;
-	
+
+	//must be 1, 5, 20, 50
+	//values >1 only available with Vdd > 2.7V
+	parameter BANDWIDTH_KHZ = 1;
+
 	//cannot simulate mixed signal IP
-	
+
 endmodule
 
 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
@@ -29,9 +33,9 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT
 	parameter VIN_ATTEN = 1;
 	parameter VIN_ISRC_EN = 0;
 	parameter HYSTERESIS = 0;
-	
+
 	initial OUT = 0;
-	
+
 	//cannot simulate mixed signal IP
 
 endmodule
@@ -40,37 +44,41 @@ module GP_BANDGAP(output reg OK);
 	parameter AUTO_PWRDN = 1;
 	parameter CHOPPER_EN = 1;
 	parameter OUT_DELAY = 100;
-	
+
 	//cannot simulate mixed signal IP
-	
+
+endmodule
+
+module GP_CLKBUF(input wire IN, output wire OUT);
+	assign OUT = IN;
 endmodule
 
 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 
-	parameter RESET_MODE 	= "RISING";	
-	
+	parameter RESET_MODE 	= "RISING";
+
 	parameter COUNT_TO		= 8'h1;
 	parameter CLKIN_DIVIDE	= 1;
-	
+
 	//more complex hard IP blocks are not supported for simulation yet
-	
+
 	reg[7:0] count = COUNT_TO;
-	
+
 	//Combinatorially output whenever we wrap low
 	always @(*) begin
 		OUT <= (count == 8'h0);
 	end
-	
+
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
 	//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
 	//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
 	always @(posedge CLK) begin
-		
+
 		count		<= count - 1'd1;
-		
+
 		if(count == 0)
 			count	<= COUNT_TO;
-			
+
 		/*
 		if((RESET_MODE == "RISING") && RST)
 			count	<= 0;
@@ -78,18 +86,18 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 			count	<= 0;
 		if((RESET_MODE == "BOTH") && RST)
 			count	<= 0;
-		*/			
+		*/
 	end
 
 endmodule
 
 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
-	parameter RESET_MODE 	= "RISING";	
-	
+	parameter RESET_MODE 	= "RISING";
+
 	parameter COUNT_TO		= 14'h1;
 	parameter CLKIN_DIVIDE	= 1;
-	
+
 	//more complex hard IP blocks are not supported for simulation yet
 
 endmodule
@@ -128,15 +136,70 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 
 endmodule
 
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
+	parameter PWRDN_SYNC = 1'b0;
+	parameter CLK_EDGE = "RISING";
+	parameter GREATER_OR_EQUAL = 1'b0;
+
+	//TODO implement power-down mode
+
+	initial GREATER = 0;
+	initial EQUAL = 0;
+
+	wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
+	always @(posedge clk_minv) begin
+		if(GREATER_OR_EQUAL)
+			GREATER <= (INP >= INN);
+		else
+			GREATER <= (INP > INN);
+
+		EQUAL <= (INP == INN);
+	end
+
+endmodule
+
+module GP_DCMPREF(output reg[7:0]OUT);
+	parameter[7:0] REF_VAL = 8'h00;
+	initial OUT = REF_VAL;
+endmodule
+
+module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
+
+	always @(*) begin
+		case(SEL)
+			2'd00: begin
+				OUTA <= IN0;
+				OUTB <= IN3;
+			end
+
+			2'd01: begin
+				OUTA <= IN1;
+				OUTB <= IN2;
+			end
+
+			2'd02: begin
+				OUTA <= IN2;
+				OUTB <= IN1;
+			end
+
+			2'd03: begin
+				OUTA <= IN3;
+				OUTB <= IN0;
+			end
+
+		endcase
+	end
+endmodule
+
 module GP_DELAY(input IN, output reg OUT);
-	
+
 	parameter DELAY_STEPS = 1;
 	parameter GLITCH_FILTER = 0;
-		
+
 	initial OUT = 0;
-	
+
 	generate
-		
+
 		//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 		//Change simulation-mode delay depending on global Vdd range (how to specify this?)
 		always @(*) begin
@@ -151,9 +214,9 @@ module GP_DELAY(input IN, output reg OUT);
 				end
 			endcase
 		end
-		
+
 	endgenerate
-	
+
 endmodule
 
 module GP_DFF(input D, CLK, output reg Q);
@@ -240,14 +303,100 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 	end
 endmodule
 
+module GP_DLATCH(input D, input nCLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHI(input D, input nCLK, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	initial nQ = INIT;
+	always @(*) begin
+		if(!nCLK)
+			nQ <= ~D;
+	end
+endmodule
+
+module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nRST)
+			Q <= 1'b0;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	initial nQ = INIT;
+	always @(*) begin
+		if(!nRST)
+			nQ <= 1'b1;
+		else if(!nCLK)
+			nQ <= ~D;
+	end
+endmodule
+
+module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSET)
+			Q <= 1'b1;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	initial nQ = INIT;
+	always @(*) begin
+		if(!nSET)
+			nQ <= 1'b0;
+		else if(!nCLK)
+			nQ <= ~D;
+	end
+endmodule
+
+module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	parameter[0:0] SRMODE = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nSR)
+			Q <= SRMODE;
+		else if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
+	parameter [0:0] INIT = 1'bx;
+	parameter[0:0] SRMODE = 1'bx;
+	initial nQ = INIT;
+	always @(*) begin
+		if(!nSR)
+			nQ <= ~SRMODE;
+		else if(!nCLK)
+			nQ <= ~D;
+	end
+endmodule
+
 module GP_EDGEDET(input IN, output reg OUT);
 
 	parameter EDGE_DIRECTION = "RISING";
 	parameter DELAY_STEPS = 1;
 	parameter GLITCH_FILTER = 0;
-	
+
 	//not implemented for simulation
-	
+
 endmodule
 
 module GP_IBUF(input IN, output OUT);
@@ -264,16 +413,16 @@ module GP_INV(input IN, output OUT);
 endmodule
 
 module GP_LFOSC(input PWRDN, output reg CLKOUT);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter OUT_DIV = 1;
-	
+
 	initial CLKOUT = 0;
-	
+
 	//auto powerdown not implemented for simulation
 	//output dividers not implemented for simulation
-	
+
 	always begin
 		if(PWRDN)
 			CLKOUT = 0;
@@ -283,7 +432,7 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
 			CLKOUT = ~CLKOUT;
 		end
 	end
-	
+
 endmodule
 
 module GP_OBUF(input IN, output OUT);
@@ -320,18 +469,22 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 			OUT <= PATTERN_DATA[count];
 
 			if( (count + 1) == PATTERN_LEN)
-				count <= 0;			
+				count <= 0;
 		end
 	end
-	
+
+endmodule
+
+module GP_PWRDET(output reg VDD_LOW);
+	initial VDD_LOW = 0;
 endmodule
 
 module GP_POR(output reg RST_DONE);
 	parameter POR_TIME = 500;
-	
+
 	initial begin
 		RST_DONE = 0;
-		
+
 		if(POR_TIME == 4)
 			#4000;
 		else if(POR_TIME == 500)
@@ -340,64 +493,64 @@ module GP_POR(output reg RST_DONE);
 			$display("ERROR: bad POR_TIME for GP_POR cell");
 			$finish;
 		end
-		
+
 		RST_DONE = 1;
-		
+
 	end
-	
+
 endmodule
 
 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter HARDIP_DIV = 1;
 	parameter FABRIC_DIV = 1;
 	parameter OSC_FREQ = "25k";
-	
+
 	initial CLKOUT_HARDIP = 0;
 	initial CLKOUT_FABRIC = 0;
-	
+
 	//output dividers not implemented for simulation
 	//auto powerdown not implemented for simulation
-	
+
 	always begin
 		if(PWRDN) begin
 			CLKOUT_HARDIP = 0;
 			CLKOUT_FABRIC = 0;
 		end
 		else begin
-		
+
 			if(OSC_FREQ == "25k") begin
 				//half period of 25 kHz
 				#20000;
 			end
-			
+
 			else begin
 				//half period of 2 MHz
 				#250;
 			end
-			
+
 			CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 		end
 	end
-	
+
 endmodule
 
 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-	
+
 	parameter PWRDN_EN = 0;
 	parameter AUTO_PWRDN = 0;
 	parameter HARDIP_DIV = 1;
 	parameter FABRIC_DIV = 1;
-	
+
 	initial CLKOUT_HARDIP = 0;
 	initial CLKOUT_FABRIC = 0;
-	
+
 	//output dividers not implemented for simulation
 	//auto powerdown not implemented for simulation
-	
+
 	always begin
 		if(PWRDN) begin
 			CLKOUT_HARDIP = 0;
@@ -410,7 +563,7 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRI
 			CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 		end
 	end
-	
+
 endmodule
 
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
@@ -418,32 +571,58 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 	parameter OUTA_TAP = 1;
 	parameter OUTA_INVERT = 0;
 	parameter OUTB_TAP = 1;
-	
+
 	reg[15:0] shreg = 0;
-	
+
 	always @(posedge CLK, negedge nRST) begin
-		
+
 		if(!nRST)
 			shreg = 0;
-		
+
 		else
 			shreg <= {shreg[14:0], IN};
-		
+
 	end
-	
+
 	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 	assign OUTB = shreg[OUTB_TAP - 1];
 
 endmodule
 
+module GP_SPI(
+	input SCK,
+	inout SDAT,
+	input CSN,
+	input[7:0] TXD_HIGH,
+	input[7:0] TXD_LOW,
+	output reg[7:0] RXD_HIGH,
+	output reg[7:0] RXD_LOW,
+	output reg INT);
+
+	initial DOUT_HIGH = 0;
+	initial DOUT_LOW = 0;
+	initial INT = 0;
+
+	parameter DATA_WIDTH = 8;		//byte or word width
+	parameter SPI_CPHA = 0;			//SPI clock phase
+	parameter SPI_CPOL = 0;			//SPI clock polarity
+	parameter DIRECTION = "INPUT";	//SPI data direction (either input to chip or output to host)
+	//parallel output to fabric not yet implemented
+
+	//TODO: write sim model
+	//TODO: SPI SDIO control... can we use ADC output while SPI is input??
+	//TODO: clock sync
+
+endmodule
+
 //keep constraint needed to prevent optimization since we have no outputs
 (* keep *)
 module GP_SYSRESET(input RST);
 	parameter RESET_MODE = "EDGE";
 	parameter EDGE_SPEED = 4;
-	
+
 	//cannot simulate whole system reset
-	
+
 endmodule
 
 module GP_VDD(output OUT);
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index ff63958e6..7d9d7d5b0 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 void invert_gp_dff(Cell *cell, bool invert_input)
 {
 	string cell_type = cell->type.str();
+	bool cell_type_latch = cell_type.find("LATCH") != string::npos;
 	bool cell_type_i = cell_type.find('I') != string::npos;
 	bool cell_type_r = cell_type.find('R') != string::npos;
 	bool cell_type_s = cell_type.find('S') != string::npos;
@@ -79,25 +80,28 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 		cell_type_i = true;
 	}
 
-	cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+	if(cell_type_latch)
+		cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+	else
+		cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
 
 	log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
 			log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
 }
 
 struct Greenpak4DffInvPass : public Pass {
-	Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFFs") { }
+	Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
 	virtual void help()
 	{
 		log("\n");
 		log("    greenpak4_dffinv [options] [selection]\n");
 		log("\n");
-		log("Merge GP_INV cells with GP_DFF* cells.\n");
+		log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header(design, "Executing GREENPAK4_DFFINV pass (merge synchronous set/reset into FF cells).\n");
+		log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -120,6 +124,15 @@ struct Greenpak4DffInvPass : public Pass {
 		gp_dff_types.insert("\\GP_DFFSR");
 		gp_dff_types.insert("\\GP_DFFSRI");
 
+		gp_dff_types.insert("\\GP_DLATCH");
+		gp_dff_types.insert("\\GP_DLATCHI");
+		gp_dff_types.insert("\\GP_DLATCHR");
+		gp_dff_types.insert("\\GP_DLATCHRI");
+		gp_dff_types.insert("\\GP_DLATCHS");
+		gp_dff_types.insert("\\GP_DLATCHSI");
+		gp_dff_types.insert("\\GP_DLATCHSR");
+		gp_dff_types.insert("\\GP_DLATCHSRI");
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 10e2a1498..be12ab495 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -36,6 +36,8 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log("    synth_greenpak4 [options]\n");
 		log("\n");
 		log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
+		log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
+		log("place-and-route.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
@@ -159,6 +161,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 			run("memory_map");
 			run("opt -undriven -fine");
 			run("techmap");
+			run("techmap -map +/greenpak4/cells_latch.v");
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)
diff --git a/tests/unit/Makefile b/tests/unit/Makefile
new file mode 100644
index 000000000..9f1e5c99e
--- /dev/null
+++ b/tests/unit/Makefile
@@ -0,0 +1,35 @@
+GTESTFLAG := -lgtest -lgtest_main
+RPATH := -Wl,-rpath
+EXTRAFLAGS := -lyosys -pthreads
+
+OBJTEST := objtest
+BINTEST := bintest
+
+ALLTESTFILE := $(shell find -name '*Test.cc' -printf '%P ')
+TESTDIRS := $(sort $(dir $(ALLTESTFILE)))
+TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o)))
+
+# Prevent make from removing our .o files
+.SECONDARY:
+
+all: prepare $(TESTS) run-tests
+
+$(BINTEST)/%: $(OBJTEST)/%.o
+	$(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) -o $@ $^ $(LDLIBS) \
+		$(GTESTFLAG) $(EXTRAFLAGS)
+
+$(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc
+	$(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $^
+
+.PHONY: prepare run-tests clean
+
+run-tests: $(TESTS)
+	$(subst Test ,Test; ,$^)
+
+prepare:
+	mkdir -p $(addprefix $(BINTEST)/,$(TESTDIRS))
+	mkdir -p $(addprefix $(OBJTEST)/,$(TESTDIRS))
+
+clean:
+	rm -rf $(OBJTEST)
+	rm -rf $(BINTEST)
diff --git a/tests/unit/kernel/logTest.cc b/tests/unit/kernel/logTest.cc
new file mode 100644
index 000000000..62b4f3b98
--- /dev/null
+++ b/tests/unit/kernel/logTest.cc
@@ -0,0 +1,14 @@
+#include <gtest/gtest.h>
+
+#include "kernel/yosys.h"
+#include "kernel/log.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(KernelLogTest, logvValidValues)
+{
+	//TODO: Implement log test
+	EXPECT_EQ(7, 7);
+}
+
+YOSYS_NAMESPACE_END
diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc
new file mode 100644
index 000000000..d9eeed555
--- /dev/null
+++ b/tests/unit/kernel/rtlilTest.cc
@@ -0,0 +1,14 @@
+#include <gtest/gtest.h>
+
+#include "kernel/yosys.h"
+#include "kernel/rtlil.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(KernelRtlilTest, getReferenceValid)
+{
+	//TODO: Implement rtlil test
+	EXPECT_EQ(33, 33);
+}
+
+YOSYS_NAMESPACE_END