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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-14 14:14:26 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-14 14:14:26 +0800 |
| commit | c77e6e6114f4489ce4801c9593e0eea42e485ae5 (patch) | |
| tree | 80c15385a538fa128e5ac3fc18085d7447489960 | |
| parent | 01d8278e539933124de1336aa8ab70f49c6ac216 (diff) | |
| download | yosys-c77e6e6114f4489ce4801c9593e0eea42e485ae5.tar.gz yosys-c77e6e6114f4489ce4801c9593e0eea42e485ae5.tar.bz2 yosys-c77e6e6114f4489ce4801c9593e0eea42e485ae5.zip | |
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1b899e8e8..b5932fef5 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -132,6 +132,29 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); endmodule +module GP_DCMPREF(output OUT) + parameter[7:0] REF_VAL = 8'h00; + wire[7:0] OUT = REF_VAL; +endmodule + +module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT) + wire[1:0] SEL; + wire[7:0] IN0; + wire[7:0] IN1; + wire[7:0] IN2; + wire[7:0] IN3; + reg[7:0] OUT; + + always @(*) begin + case(SEL) + 2'b00: OUT <= IN0; + 2'b10: OUT <= IN1; + 2'b01: OUT <= IN2; + 2'b11: OUT <= IN3; + end + end +endmodule + module GP_DELAY(input IN, output reg OUT); parameter DELAY_STEPS = 1; |