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| * | | Merge pull request #1200 from mmicko/fix_typo_liberty_ccClifford Wolf2019-07-161-1/+1
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| | * | | Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
| * | | | Merge pull request #1199 from mmicko/extract_fa_fixClifford Wolf2019-07-161-2/+2
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| | * | | Fix check logic in extract_faMiodrag Milanovic2019-07-161-2/+2
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| * | | Merge pull request #1196 from YosysHQ/eddie/fix1178Eddie Hung2019-07-151-5/+12
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| | * | | Revert "Add log_checkpoint function and use it in opt_muxtree"Eddie Hung2019-07-153-9/+0
| | * | | Revert "Fix first divergence in #1178"Eddie Hung2019-07-151-5/+1
| | * | | Merge branch 'master' into eddie/fix1178Eddie Hung2019-07-1526-93/+1204
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| | * | | | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ...Clifford Wolf2019-07-151-6/+13
| | * | | | Add log_checkpoint function and use it in opt_muxtreeClifford Wolf2019-07-153-0/+9
| | * | | | Fix first divergence in #1178Eddie Hung2019-07-091-1/+5
| * | | | | Merge pull request #1189 from YosysHQ/eddie/fix1151Clifford Wolf2019-07-151-0/+4
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| | * | | | | Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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| * | | | | Merge pull request #1190 from YosysHQ/eddie/fix_1099Clifford Wolf2019-07-151-4/+8
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| | * | | | | If ConstEval fails do not log_abort() but return gracefullyEddie Hung2019-07-131-4/+8
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| * | | | | Merge pull request #1191 from whitequark/opt_lut-log_debugClifford Wolf2019-07-151-56/+38
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| | * | | | | opt_lut: make less chatty.whitequark2019-07-131-56/+38
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| * | | | | Merge pull request #1195 from Roman-Parise/masterClifford Wolf2019-07-151-1/+1
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| | * | | | | Updated FreeBSD dependencies in README.mdRoman-Parise2019-07-141-1/+1
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| * | | | | Merge pull request #1197 from nakengelhardt/handle-setrlimit-failClifford Wolf2019-07-151-1/+5
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| | * | | | smt: handle failure of setrlimit syscallN. Engelhardt2019-07-151-1/+5
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* | | | | ice40_dsp to accept $__MUL16X16 tooEddie Hung2019-07-181-1/+1
* | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
* | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
* | | | | Check if RHS is empty firstEddie Hung2019-07-181-0/+2
* | | | | Make consistentEddie Hung2019-07-181-1/+2
* | | | | Do not autoremove ffP aor muxPEddie Hung2019-07-181-2/+0
* | | | | Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-182-12/+22
* | | | | Improve A/B reg packingEddie Hung2019-07-182-6/+11
* | | | | Do not autoremove A/B registers since they might have other consumersEddie Hung2019-07-181-2/+0
* | | | | Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
* | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
* | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
* | | | | Working for unsignedEddie Hung2019-07-181-52/+28
* | | | | CleanupEddie Hung2019-07-181-70/+58
* | | | | Wrong wildcard symbolEddie Hung2019-07-181-1/+1
* | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| * | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
* | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
* | | | | | Update commentEddie Hung2019-07-171-5/+3
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* | | | | Pattern matcher to check pool of bits, not exactlyEddie Hung2019-07-172-5/+11
* | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
* | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
* | | | | SigSpec::remove_const() to return SigSpec&Eddie Hung2019-07-172-2/+3
* | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
* | | | | SignednessEddie Hung2019-07-162-8/+8
* | | | | Signed extensionEddie Hung2019-07-162-6/+6
* | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
* | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| * | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1