iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix warnings	Eddie Hung	2019-12-31	2	-2/+2
*	Call equiv_opt with -multiclock and -assert	Eddie Hung	2019-12-31	5	-5/+5
*	Grammar	Eddie Hung	2019-12-30	1	-1/+1
*	Update timings for Xilinx S7 cells	Eddie Hung	2019-12-30	1	-15/+35
*	Merge pull request #1589 from YosysHQ/iopad_default	Miodrag Milanović	2019-12-30	20	-71/+67
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\| *	Fix new tests	Miodrag Milanovic	2019-12-28	3	-6/+6
\| *	Merge remote-tracking branch 'origin/master' into iopad_default	Miodrag Milanovic	2019-12-28	20	-150/+1614
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\| * \|	Make test without iopads	Miodrag Milanovic	2019-12-28	17	-51/+51
\| * \|	Revert "Fix xilinx tests, when iopads are default"	Miodrag Milanovic	2019-12-28	16	-40/+40
\| * \|	Addressed review comments	Miodrag Milanovic	2019-12-21	2	-3/+3
\| * \|	iopad no op for compatibility with old scripts	Miodrag Milanovic	2019-12-21	1	-0/+3
\| * \|	Fix xilinx tests, when iopads are default	Miodrag Milanovic	2019-12-21	17	-42/+44
\| * \|	Make iopad option default for all xilinx flows	Miodrag Milanovic	2019-12-21	1	-14/+5
* \| \|	Merge pull request #1599 from YosysHQ/eddie/retry_1588	Eddie Hung	2019-12-30	4	-20/+87
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\| * \| \|	Add #1598 testcase	Eddie Hung	2019-12-27	3	-0/+48
\| * \| \|	write_xaiger: inherit port ordering from original module	Eddie Hung	2019-12-27	1	-5/+16
\| * \| \|	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"	Eddie Hung	2019-12-27	1	-19/+27
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* \| \|	Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5	Eddie Hung	2019-12-30	3	-14/+6
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\| * \|	Update resource count	Eddie Hung	2019-12-28	1	-3/+3
\| * \|	Nitpick cleanup for ecp5	Eddie Hung	2019-12-27	2	-11/+3
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* \|	Merge branch 'master' of github.com:YosysHQ/yosys	Eddie Hung	2019-12-27	1	-27/+19
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\| * \	Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup	David Shah	2019-12-27	1	-27/+19
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\| \| * \|	Revert "write_xaiger: only instantiate each whitebox cell type once"	David Shah	2019-12-27	1	-27/+19
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* / /	write_xaiger: simplify c{i,o}_bits	Eddie Hung	2019-12-27	1	-12/+6
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* \|	fixed invalid char	Miodrag Milanovic	2019-12-25	1	-1/+1
* \|	iopadmap: Emit tristate buffers with const OE for some edge cases.	Marcin Kościelnicki	2019-12-25	2	-23/+91
* \|	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen	Marcin Kościelnicki	2019-12-25	12	-81/+1136
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\| * \|	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
\| * \|	Add DSP cascade tests	Eddie Hung	2019-12-23	1	-0/+89
\| * \|	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
\| * \|	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
\| * \|	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
\| * \|	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
\| * \|	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10
\| * \|	xilinx_dsp: Initial DSP48A/DSP48A1 support.	Marcin Kościelnicki	2019-12-22	10	-14/+921
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* /	xilinx: Test our DSP48A/DSP48A1 simulation models.	Marcin Kościelnicki	2019-12-23	5	-7/+362
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*	Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-20	1	-19/+27
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\| *	write_xaiger: only instantiate each whitebox cell type once	Eddie Hung	2019-12-20	1	-19/+27
* \|	Add abc9_arrival times for RAM{32,64}M	Eddie Hung	2019-12-20	1	-24/+10
* \|	Add RAM{32,64}M to abc9_map.v	Eddie Hung	2019-12-20	1	-0/+78
* \|	Put specify/endspecify inside ``	Eddie Hung	2019-12-20	1	-4/+4
* \|	Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut	Eddie Hung	2019-12-20	1	-19/+18
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\| *	Interpret "abc9 -lut" as lut string only if [0-9:]	Eddie Hung	2019-12-18	1	-19/+18
* \|	Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup	Eddie Hung	2019-12-20	4	-39/+21
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\| * \|	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	4	-39/+21
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* \|	Fix linking with Python 3.8	Graham Edgecombe	2019-12-20	1	-0/+7
* \|	Add PYTHON_CONFIG variable to the Makefile	Graham Edgecombe	2019-12-20	1	-17/+18
* \|	Merge pull request #1581 from YosysHQ/clifford/fix1565	Eddie Hung	2019-12-19	1	-1/+1
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\| * \|	Fix sim for assignments with lhs<rhs size, fixes #1565	Clifford Wolf	2019-12-17	1	-1/+1
* \| \|	Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup	Eddie Hung	2019-12-19	4	-21/+39
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