| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |/ / / /
| | | | |
| | | | |
| | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\ \ \ \ \
| |_|/ / /
|/| | | | |
Improve ABC netname preservation
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: David Shah <davey1576@gmail.com>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: David Shah <davey1576@gmail.com>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: David Shah <davey1576@gmail.com>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: David Shah <dave@ds0.me>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\ \ \ \ \
| | | | | |
| | | | | | |
Add -params mode to force undef parameters in selected cells.
|
|/ / / / /
| | | | |
| | | | |
| | | | | |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
|
|\ \ \ \ \
| | | | | |
| | | | | | |
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
|
| | |/ / /
| |/| | |
| | | | |
| | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\ \ \ \ \
| | | | | |
| | | | | | |
Pattern Matcher Generator and iCE40 DSP Mapper
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| |\ \ \ \ \ |
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\ \ \ \ \ \ \
| |_|_|/ / / /
|/| | | | | | |
Revert "Add -B option to autotest.sh to append to backend_opts"
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
|
|\| | | | | |
| | | | | | |
| | | | | | | |
Cleanup #805
|
| | | | | | | |
|
|\| | | | | |
| |_|/ / / /
|/| | | | | |
write_verilog to write initial statement for initial flop state
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
per @cliffordwolf
|
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.
|
| |\ \ \ \ \
| |/ / / / /
|/| | | | | |
|
|\ \ \ \ \ \
| |_|_|_|/ /
|/| | | | | |
Update cells supported for verilog to FIRRTL conversion.
|
| | | | | | |
|
| | | | | | |
|
|/ / / / /
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
|\ \ \ \ \
| | | | | |
| | | | | | |
write_verilog: correctly emit asynchronous transparent ports
|
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | |
| | | | | | |
This commit fixes two related issues:
* For asynchronous ports, clock is no longer added to domain list.
(This would lead to absurd constructs like `always @(posedge 0)`.
* The logic to distinguish synchronous and asynchronous ports is
changed to correctly use or avoid clock in all cases.
Before this commit, the following RTLIL snippet (after memory_collect)
cell $memrd $2
parameter \MEMID "\\mem"
parameter \ABITS 2
parameter \WIDTH 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 1
parameter \TRANSPARENT 1
connect \CLK 1'0
connect \EN 1'1
connect \ADDR \mem_r_addr
connect \DATA \mem_r_data
end
would lead to invalid Verilog:
reg [1:0] _0_;
always @(posedge 1'h0) begin
_0_ <= mem_r_addr;
end
assign mem_r_data = mem[_0_];
Note that there are two potential pitfalls remaining after this
change:
* For asynchronous ports, the \EN input and \TRANSPARENT parameter
are silently ignored. (Per discussion in #760 this is the correct
behavior.)
* For synchronous transparent ports, the \EN input is ignored. This
matches the behavior of the $mem simulation cell. Again, see #760.
|
|\ \ \ \ \ \
| |_|_|_|/ /
|/| | | | | |
fsm_opt: Fix runtime error for FSMs without a reset state
|
|/ / / / /
| | | | |
| | | | |
| | | | | |
Signed-off-by: David Shah <dave@ds0.me>
|
| | | | | |
|
| | | | | |
|
| | | | | |
|