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* rpc: new frontend.whitequark2019-09-309-0/+744
| | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
* libs: import json11.whitequark2019-09-303-0/+1023
| | | | | This commit imports the code from upstream commit dropbox/json11@8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
* Missing an '&'Eddie Hung2019-09-261-1/+1
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* Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40Eddie Hung2019-09-252-19/+14
|\ | | | | ICE40 tests. adffs test update (equiv_opt -multiclock).
| * Change sync controls to async.SergeyDegtyar2019-09-252-8/+8
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| * adffs test update (equiv_opt -multiclock).SergeyDegtyar2019-09-242-18/+13
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* | Merge pull request #1402 from YosysHQ/clifford/portlistClifford Wolf2019-09-252-0/+94
|\ \ | | | | | | Add "portlist" command
| * | Improve "portlist" commandClifford Wolf2019-09-251-9/+26
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "portlist" commandClifford Wolf2019-09-242-0/+77
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1399 from nakengelhardt/fix-show-macosMiodrag Milanović2019-09-232-0/+9
|\ \ | | | | | | fix show command for macos
| * | add xdot dependency to BrewfileN. Engelhardt2019-09-231-0/+1
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| * | fix show command for macosN. Engelhardt2019-09-231-0/+8
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* | Merge pull request #1392 from YosysHQ/eddie/fix1391Clifford Wolf2019-09-212-1/+69
|\ \ | | | | | | (* techmap_autopurge *) fixes when ports aren't consistently-sized
| * | Hell let's add the original #1381 testcase tooEddie Hung2019-09-201-3/+22
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| * | Revert abc9.ccEddie Hung2019-09-201-1/+1
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| * | Add testcaseEddie Hung2019-09-201-0/+43
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| * | Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
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| * | Fix first testcase in #1391Eddie Hung2019-09-202-2/+2
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* | Merge pull request #1386 from YosysHQ/clifford/fix1360Clifford Wolf2019-09-202-18/+30
|\ \ | | | | | | Fix handling of read_verilog config in AstModule::reprocess_module()
| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-202-18/+30
|/ / | | | | | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Update CHANGELOGClifford Wolf2019-09-201-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "add -mod"Clifford Wolf2019-09-201-0/+18
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1384 from YosysHQ/clifford/fix1381Clifford Wolf2019-09-201-5/+49
|\ \ | | | | | | Add techmap_autopurge attribute
| * | Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
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* | Added extractinv passMarcin Kościelnicki2019-09-195-0/+172
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* | Document (* gentb_skip *) attr for test_autotbEddie Hung2019-09-181-0/+3
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* | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxextEddie Hung2019-09-186-14/+291
|\ \ | | | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
| * | OopsEddie Hung2019-09-131-1/+1
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| * | Add counter-example from @cliffordwolfEddie Hung2019-09-131-0/+24
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| * | Revert "Make one check $shift(x)? only; change testcase to be 8b"Eddie Hung2019-09-132-5/+4
| | | | | | | | | | | | This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80.
| * | Tidy upEddie Hung2019-09-111-10/+16
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| * | Fix UBEddie Hung2019-09-111-2/+2
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| * | Cope with presence of reset muxes tooEddie Hung2019-09-112-4/+64
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| * | CleanupEddie Hung2019-09-111-25/+22
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| * | Add more testsEddie Hung2019-09-111-0/+32
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| * | Only display log message if did_somethingEddie Hung2019-09-111-1/+1
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| * | Rename dffmuxext -> dffmux, also remove constants in dff+muxEddie Hung2019-09-114-57/+91
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| * | proc instead of prepEddie Hung2019-09-111-2/+2
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| * | Add unsigned caseEddie Hung2019-09-111-0/+17
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| * | Missing equiv_opt -assertEddie Hung2019-09-061-1/+1
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| * | Make one check $shift(x)? only; change testcase to be 8bEddie Hung2019-09-062-4/+5
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| * | Usee equiv_opt -assertEddie Hung2019-09-061-3/+3
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| * | simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-052-21/+63
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| * | Revert "abc9 followed by clean otherwise netlist could be invalid for sim"Eddie Hung2019-09-051-1/+0
| | | | | | | | | | | | This reverts commit 6fe1ca633d90fb238d2671dba3d7f772c263a497.
| * | Revert "parse_xaiger() to do "clean -purge""Eddie Hung2019-09-041-1/+1
| | | | | | | | | | | | This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5.
| * | abc9 followed by clean otherwise netlist could be invalid for simEddie Hung2019-09-041-0/+1
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| * | Remove log_cell() callsEddie Hung2019-09-041-3/+0
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| * | Add peepopt_dffmuxextEddie Hung2019-09-043-0/+60
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| * | Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
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