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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 11:13:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 11:13:08 -0700 |
| commit | 143f82def2030527a4fa92b7ba60b704aad08e53 (patch) | |
| tree | 1a07c949e32bbfa017a919185777f2e7fff3d4a9 | |
| parent | a009314597b2d71cb786745c516e53dff4b21a00 (diff) | |
| download | yosys-143f82def2030527a4fa92b7ba60b704aad08e53.tar.gz yosys-143f82def2030527a4fa92b7ba60b704aad08e53.tar.bz2 yosys-143f82def2030527a4fa92b7ba60b704aad08e53.zip | |
Missing an '&'
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 173841799..888b5ed7b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); - if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s") + if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s") log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); if (widemux != 0 && widemux < 2) |