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authorEddie Hung <eddie@fpgeh.com>2019-09-20 17:49:26 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-20 17:51:45 -0700
commit6258e6a7e28ade2bdc7b6809675461326c873a45 (patch)
tree29fc09cdd52e19dda564be260bfdf41af8664643
parent72ce06909e87d1697ed5eac62d91db00a751a34b (diff)
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Add testcase
-rw-r--r--tests/techmap/autopurge.ys43
1 files changed, 43 insertions, 0 deletions
diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..4773d5ce3
--- /dev/null
+++ b/tests/techmap/autopurge.ys
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+# https://github.com/YosysHQ/yosys/issues/1391
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy