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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:21:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:21:39 -0700 |
| commit | d3eea82bc27f6e54b6c1e05a73be8456344ec8b7 (patch) | |
| tree | 6894b76d6190ff9c3a4e459a6ca5ff25f3512dbf | |
| parent | 6fe1ca633d90fb238d2671dba3d7f772c263a497 (diff) | |
| download | yosys-d3eea82bc27f6e54b6c1e05a73be8456344ec8b7.tar.gz yosys-d3eea82bc27f6e54b6c1e05a73be8456344ec8b7.tar.bz2 yosys-d3eea82bc27f6e54b6c1e05a73be8456344ec8b7.zip | |
Revert "parse_xaiger() to do "clean -purge""
This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5.
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2e1fb8fad..06522939f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -974,7 +974,7 @@ void AigerReader::post_process() // operate (and run checks on) this one module RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); - Pass::call(mapped_design, "clean -purge"); + Pass::call(mapped_design, "clean"); mapped_design->modules_.erase(module->name); delete mapped_design; |