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* | | Bump versionYosys Bot2021-02-071-1/+1
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* | | Merge pull request #2576 from zachjs/port-bind-sign-uniopwhitequark2021-02-063-8/+33
|\ \ \ | | | | | | | | genrtlil: fix signed port connection codegen failures
| * | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-053-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | | | Bump versionYosys Bot2021-02-061-1/+1
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* | | Merge pull request #2572 from antmicro/check-labelswhitequark2021-02-052-0/+28
|\ \ \ | | | | | | | | verilog_parser: add label check to gen_block
| * | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-042-0/+28
| |/ / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* / / Bump versionYosys Bot2021-02-051-1/+1
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* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0433-258/+779
|\ \ | | | | | | verilog: significant block scoping improvements
| * | verilog: significant block scoping improvementsZachary Snow2021-01-3133-258/+779
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | | Bump versionYosys Bot2021-02-041-1/+1
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* | | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
|\ \ \ | | | | | | | | Fix begin/end in generate
| * | | Fix begin/end in generatedalance2020-11-112-7/+4
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* | | | Bump versionYosys Bot2021-01-311-1/+1
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* | | | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
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* | | | Bump versionYosys Bot2021-01-301-1/+1
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* | | | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* | | | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
|\ \ \ \ | | | | | | | | | | flatten: clarify confusing error message
| * | | | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
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* | | | | Bump versionYosys Bot2021-01-291-1/+1
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* | | | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaceswhitequark2021-01-282-1/+25
|\ \ \ \ \ | | | | | | | | | | | | verilog: strip leading and trailing spaces in macro args
| * | | | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-282-1/+25
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* | | | | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-282-18/+61
|\ \ \ \ \ | |/ / / / |/| | | | scc: Add -specify option to find loops in boxes
| * | | | scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-262-18/+61
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* | | | | Bump versionYosys Bot2021-01-271-1/+1
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* | | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-273-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | | | | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* | | | | Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: do not use `->template` for non-dependent names
| * | | | | cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | |/ / / | |/| | | | | | | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | | | | Merge pull request #2544 from modwizcode/fix-clockwhitequark2021-01-261-7/+15
|\ \ \ \ \ | |/ / / / |/| | | | CXXRTL: Fix sliced bits as clock inputs
| * | | | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
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| * | | | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* | | | | Bump versionYosys Bot2021-01-261-1/+1
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* | | | | Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ \ \ \ \ | | | | | | | | | | | | adding support for passing multiple liberty files to abc
| * | | | | adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
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* | | | | | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-252-1/+28
|\ \ \ \ \ \ | | | | | | | | | | | | | | verilog: allow spaces in macro arguments
| * | | | | | verilog: allow spaces in macro argumentsZachary Snow2021-01-202-1/+28
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* | | | | | Bump versionYosys Bot2021-01-251-1/+1
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* | | | | | Merge pull request #2558 from YosysHQ/dave/chandle-dpiClaire Xen2021-01-241-1/+16
|\ \ \ \ \ \ | | | | | | | | | | | | | | dpi: Support for chandle type
| * | | | | | dpi: Support for chandle typeDavid Shah2021-01-231-1/+16
|/ / / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Bump versionYosys Bot2021-01-221-1/+1
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* | | | | | Merge pull request #2553 from zachjs/rand-const-modifiersMiodrag Milanović2021-01-213-2/+19
|\ \ \ \ \ \ | | | | | | | | | | | | | | Allow combination of rand and const modifiers
| * | | | | | Allow combination of rand and const modifiersZachary Snow2021-01-213-2/+19
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* | | | | | Bump versionYosys Bot2021-01-211-1/+1
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* | | | | | Merge pull request #2552 from YosysHQ/claire/yosyshqClaire Xen2021-01-211-18/+18
|\ \ \ \ \ \ | | | | | | | | | | | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
| * | | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵Claire Xenia Wolf2021-01-201-18/+18
|/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | | | Merge pull request #2536 from TobiasFaller/masterMiodrag Milanović2021-01-201-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Fixed missing goto statement in passes/techmap/abc.cc
| * | | | | | Fixed missing goto statement in passes/techmap/abc.ccTobias Faller2021-01-121-0/+1
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* | | | | | Merge pull request #2551 from zachjs/wire-logicMiodrag Milanović2021-01-203-9/+65
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | sv: fix support wire and var data type modifiers
| * | | | | sv: fix support wire and var data type modifiersZachary Snow2021-01-203-9/+65
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* | | | | Bump versionYosys Bot2021-01-191-1/+1
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