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authorZachary Snow <zach@zachjs.com>2021-01-21 08:30:55 -0700
committerZachary Snow <zach@zachjs.com>2021-01-21 08:42:05 -0700
commit1096b969efb24dc28b501585f23ceb242d781745 (patch)
tree2d887c1512458456391bb6c098f2dc2eba46db90
parent699a98b265a41b0565637323f929e6cb1f8837e0 (diff)
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Allow combination of rand and const modifiers
-rw-r--r--frontends/verilog/verilog_parser.y12
-rw-r--r--tests/various/rand_const.sv8
-rw-r--r--tests/various/rand_const.ys1
3 files changed, 19 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2886db0e5..8bd58d24c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -651,8 +651,16 @@ wire_type_signedness:
%empty;
wire_type_const_rand:
- TOK_CONST { current_wire_const = true; } |
- TOK_RAND { current_wire_rand = true; } |
+ TOK_RAND TOK_CONST {
+ current_wire_rand = true;
+ current_wire_const = true;
+ } |
+ TOK_CONST {
+ current_wire_const = true;
+ } |
+ TOK_RAND {
+ current_wire_rand = true;
+ } |
%empty;
opt_wire_type_token:
diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv
new file mode 100644
index 000000000..be00812c0
--- /dev/null
+++ b/tests/various/rand_const.sv
@@ -0,0 +1,8 @@
+module top;
+ rand const reg rx;
+ const reg ry;
+ rand reg rz;
+ rand const integer ix;
+ const integer iy;
+ rand integer iz;
+endmodule
diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys
new file mode 100644
index 000000000..74e43c7cc
--- /dev/null
+++ b/tests/various/rand_const.ys
@@ -0,0 +1 @@
+read_verilog -sv rand_const.sv