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* Removed $bu0 cell typeClifford Wolf2014-09-0418-103/+27
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* Using $pos models for $bu0Clifford Wolf2014-09-033-18/+3
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* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
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* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-032-6/+5
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* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
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* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
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* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
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* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-022-2/+1
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* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-023-9/+8
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* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
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* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-024-24/+12
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* Removed yosys-svgviewerClifford Wolf2014-09-0214-1121/+18
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* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-022-5/+4
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* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
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* Added ConstEval model for $alu cellsClifford Wolf2014-09-011-0/+56
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* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
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* Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
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* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
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* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
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* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
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* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-014-38/+35
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* Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
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* Fixed return size of const_*() eval functionsClifford Wolf2014-08-311-1/+5
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* Added RTLIL::Const::size()Clifford Wolf2014-08-311-0/+2
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* Added eval model for $lut cellsClifford Wolf2014-08-311-0/+26
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* Typo fixes in cell->*Param() APIClifford Wolf2014-08-311-4/+4
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-314-9/+102
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* Added design->scratchpadClifford Wolf2014-08-3010-64/+91
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* Added $alu cell typeClifford Wolf2014-08-305-3/+67
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* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-303-4/+6
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* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
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* Fixed module->addPmux()Clifford Wolf2014-08-301-1/+0
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* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
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* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-301-32/+28
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* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
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* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
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* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
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* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
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* Fixed printing of multi-line Makefile.confClifford Wolf2014-08-271-1/+6
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* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
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* Print Makefile.conf as make info messageClifford Wolf2014-08-261-1/+4
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* Checking for valid CONFIG value in MakefileClifford Wolf2014-08-251-6/+6
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* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
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* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
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* Added is_signed argument to SigSpec.as_int() and Const.as_int()Clifford Wolf2014-08-242-6/+9
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* azonenberg: Make dump_vcd save model when temporal induction fails due to ↵Clifford Wolf2014-08-241-0/+2
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* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
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* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-238-195/+21
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-2322-89/+116
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