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authorClifford Wolf <clifford@clifford.at>2014-09-01 16:36:04 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-01 16:36:04 +0200
commit630befdf6d58ab5f7c4ca1ea77c86df7b88ee259 (patch)
tree4813828a208d9cbcaeabb84a95e128695723e057
parent2fcf66b91d324758eb58807592702b6844bd37ab (diff)
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Added $alu support to test_cell
-rw-r--r--passes/tests/test_cell.cc23
1 files changed, 22 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 7f9f1f9b8..7c7d6b7fd 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -95,6 +95,27 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort("\\Y", wire);
}
+ if (cell_type == "$alu")
+ {
+ wire = module->addWire("\\CI");
+ wire->port_input = true;
+ cell->setPort("\\CI", wire);
+
+ wire = module->addWire("\\BI");
+ wire->port_input = true;
+ cell->setPort("\\BI", wire);
+
+ wire = module->addWire("\\X");
+ wire->width = SIZE(cell->getPort("\\Y"));
+ wire->port_output = true;
+ cell->setPort("\\X", wire);
+
+ wire = module->addWire("\\CO");
+ wire->width = SIZE(cell->getPort("\\Y"));
+ wire->port_output = true;
+ cell->setPort("\\CO", wire);
+ }
+
module->fixup_ports();
cell->fixup_parameters();
cell->check();
@@ -317,7 +338,7 @@ struct TestCellPass : public Pass {
// cell_types["$assert"] = "A";
cell_types["$lut"] = "*";
- // cell_types["$alu"] = "*";
+ cell_types["$alu"] = "ABSY";
for (; argidx < SIZE(args); argidx++)
{