iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	18	-103/+27
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03	3	-18/+3
*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03	1	-4/+6
*	Fixes in $alu SAT- and eval-models	Clifford Wolf	2014-09-03	2	-6/+5
*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02	1	-3/+6
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02	1	-3/+8
*	Added test_cell -vlog	Clifford Wolf	2014-09-02	1	-2/+79
*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02	2	-2/+1
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	3	-9/+8
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02	1	-1/+89
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	4	-24/+12
*	Removed yosys-svgviewer	Clifford Wolf	2014-09-02	14	-1121/+18
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	2	-5/+4
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01	1	-1/+22
*	Added ConstEval model for $alu cells	Clifford Wolf	2014-09-01	1	-0/+56
*	Added SAT model for $alu cells	Clifford Wolf	2014-09-01	1	-2/+69
*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01	1	-2/+3
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01	1	-8/+29
*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01	1	-2/+18
*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01	1	-3/+4
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	5	-2/+2
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	4	-38/+35
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31	1	-0/+88
*	Fixed return size of const_*() eval functions	Clifford Wolf	2014-08-31	1	-1/+5
*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31	1	-0/+2
*	Added eval model for $lut cells	Clifford Wolf	2014-08-31	1	-0/+26
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31	1	-4/+4
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	4	-9/+102
*	Added design->scratchpad	Clifford Wolf	2014-08-30	10	-64/+91
*	Added $alu cell type	Clifford Wolf	2014-08-30	5	-3/+67
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30	3	-4/+6
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30	1	-16/+28
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30	1	-1/+0
*	Using worker class in memory_map	Clifford Wolf	2014-08-30	1	-226/+231
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30	1	-32/+28
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30	1	-1/+6
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30	1	-0/+10
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30	1	-20/+75
*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27	1	-0/+5
*	Fixed printing of multi-line Makefile.conf	Clifford Wolf	2014-08-27	1	-1/+6
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26	1	-4/+13
*	Print Makefile.conf as make info message	Clifford Wolf	2014-08-26	1	-1/+4
*	Checking for valid CONFIG value in Makefile	Clifford Wolf	2014-08-25	1	-6/+6
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24	1	-0/+35
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24	1	-1/+10
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	2	-6/+9
*	azonenberg: Make dump_vcd save model when temporal induction fails due to ste...	Clifford Wolf	2014-08-24	1	-0/+2
*	Only call proc_share_dirname() in techmap when necessary	Clifford Wolf	2014-08-23	1	-2/+1
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23	8	-195/+21
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	22	-89/+116