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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:17:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-30 18:17:22 +0200 |
| commit | dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa (patch) | |
| tree | 535ffeae7eb1e549413bc174a9c5a50af9ad06e9 | |
| parent | 66763fad4e3f93b11fbc72acd94174a56084ad17 (diff) | |
| download | yosys-dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa.tar.gz yosys-dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa.tar.bz2 yosys-dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa.zip | |
Fixed module->addPmux()
| -rw-r--r-- | kernel/rtlil.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index df4d8b092..7ba6911a2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1309,7 +1309,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or") RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\WIDTH"] = sig_a.size(); \ - cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ cell->setPort("\\A", sig_a); \ cell->setPort("\\B", sig_b); \ |