| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 |
| * | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 |
| * | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 |
| * | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 |
| * | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| * | Add CHANGELOG entry | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
| * | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 |
| * | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 |
| * | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 |
| * | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| * | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 |
| * | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 19 | -102/+1046 |
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| | * | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 2 | -4/+96 |
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| | | * | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
| | | * | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -1/+15 |
| | | * | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 2 | -5/+51 |
| | | * | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
| | | * | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 |
| | | * | Add test | Eddie Hung | 2019-08-21 | 1 | -0/+14 |
| | | * | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
| | * | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 3 | -3/+3 |
| | * | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 |
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| | | * \ | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 109 | -3621/+4745 |
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| | | * | | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 |
| | * | | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | * | | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 |
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| | | * | | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
| | | * | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
| | | * | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
| | | * | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
| | | * | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 |
| | | * | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 |
| | | * | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 |
| | | * | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 58 | -598/+1321 |
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| | | * | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 |
| | | * | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 |
| | | * | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 |
| | | * | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 |
| * | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
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| | * | | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg | Clifford Wolf | 2019-08-22 | 2 | -0/+17 |
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| | * \ \ \ \ \ \ | Merge pull request #1315 from mmicko/fix_dependencies | whitequark | 2019-08-21 | 1 | -1/+1 |
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| | | * | | | | | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 |
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| * | | | | | | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| * | | | | | | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 |
| * | | | | | | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
| * | | | | | | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 |
| * | | | | | | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
| * | | | | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -18/+167 |
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index : iCE40/yosys | |
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