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* synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
* synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
* xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
* xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
* Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
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| * update testPepijn de Vos2019-12-031-2/+3
| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-032-11/+13
| * attempt to fix formattingPepijn de Vos2019-11-252-292/+292
| * gowin: add and test dff init valuesPepijn de Vos2019-11-254-41/+495
* | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fixDavid Shah2019-12-022-29/+46
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| * | abc9: Fix breaking of SCCsDavid Shah2019-12-012-29/+46
* | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-checkClifford Wolf2019-12-011-0/+4
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| * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
* | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpllMiodrag Milanović2019-11-292-0/+21
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| * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
* | | | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
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* | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-272-3/+72
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| * | | No need for -abc9Eddie Hung2019-11-261-1/+1
| * | | Add citationEddie Hung2019-11-261-0/+1
| * | | Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
| * | | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
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* | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
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| * | | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
* | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-272-4/+24
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| * | | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-272-4/+24
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* | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improveEddie Hung2019-11-272-22/+5
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| * | | latch -> boxEddie Hung2019-11-261-1/+1
| * | | Remove notesEddie Hung2019-11-261-9/+0
| * | | Fold loopEddie Hung2019-11-261-6/+3
| * | | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
| * | | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
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* | | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
* | | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-254-6/+69
* | | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-255-10/+14
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* | Merge pull request #1520 from pietrmar/fix-1463Eddie Hung2019-11-221-2/+0
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| * | coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
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* | Merge pull request #1517 from YosysHQ/clifford/optmemClifford Wolf2019-11-223-0/+146
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| * | Add "opt_mem" passClifford Wolf2019-11-223-0/+146
* | | Merge pull request #1515 from YosysHQ/clifford/svastuffClifford Wolf2019-11-222-7/+39
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| * | Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| * | Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| * | Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
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* | Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-226-9/+126
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| * | Update CHANGELOG and READMEDavid Shah2019-11-222-0/+7
| * | sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| * | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usageDavid Shah2019-11-211-4/+16
| * | sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
* | | gowin: Remove show command from tests.Marcin Kościelnicki2019-11-221-1/+0
* | | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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