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* Faster "make clean-abc"Clifford Wolf2015-01-201-2/+2
* README stuffClifford Wolf2015-01-201-2/+3
* Added equiv_simpleClifford Wolf2015-01-192-0/+188
* Added equiv_statusClifford Wolf2015-01-192-0/+95
* Added equiv_make commandClifford Wolf2015-01-194-1/+260
* Added $equiv cell typeClifford Wolf2015-01-194-2/+33
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-01-181-0/+6
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| * Merge pull request #47 from mschmoelzer/masterClifford Wolf2015-01-181-0/+6
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| | * Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.Martin Schmölzer2015-01-181-0/+6
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* | Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
* | Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-186-674/+466
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* improvements in muxtree/select_leaves testClifford Wolf2015-01-181-2/+5
* Improvements in opt_muxtreeClifford Wolf2015-01-182-35/+58
* More opt_muxtree cleanupsClifford Wolf2015-01-181-64/+44
* Added hashlib::idict<>Clifford Wolf2015-01-183-2/+73
* Various cleanups and improvements in opt_muxtreeClifford Wolf2015-01-181-87/+71
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
* Added support for memories to flatten (techmap)Clifford Wolf2015-01-171-3/+22
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-174-2/+106
* Fixed a bug in opt_muxtree for "mux forests"Clifford Wolf2015-01-171-4/+18
* Improved opt_muxtreeClifford Wolf2015-01-171-4/+38
* Optimizing no-op cell->setPort()Clifford Wolf2015-01-171-1/+3
* Bugfix in dff2dffeClifford Wolf2015-01-161-1/+1
* Added cells.libClifford Wolf2015-01-162-0/+109
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-161-0/+2
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-161-25/+28
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-161-21/+35
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-161-116/+116
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-152-2/+30
* Added "abc -lut w1:w2"Clifford Wolf2015-01-151-5/+21
* Fixed handling of foo.__TECHMAP_...Clifford Wolf2015-01-151-1/+1
* Ignoring more system task and functionsClifford Wolf2015-01-152-2/+4
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-131-54/+8
* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-131-5/+0
* Tiny fix in vcdcd.plClifford Wolf2015-01-131-2/+2
* Small Makefile typo fixClifford Wolf2015-01-131-2/+2
* Only enable code coverage counters on linuxClifford Wolf2015-01-094-6/+6
* Merge pull request #46 from utzig/masterClifford Wolf2015-01-083-5/+11
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| * Enable use of homebrew's provided bison if availableFabio Utzig2015-01-081-0/+2
| * Enable bison to be customizedFabio Utzig2015-01-083-2/+3
| * Add homebrew's libffi pathsFabio Utzig2015-01-081-0/+3
| * Add homebrew's readline pathsFabio Utzig2015-01-081-3/+3
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* Added add_share_file Makefile macroClifford Wolf2015-01-083-38/+17
* added minimalistic xilinx sim modelsClifford Wolf2015-01-081-0/+150
* disabled problematic mux -> and/or transformClifford Wolf2015-01-071-2/+7
* More Xilinx bram cleanupsClifford Wolf2015-01-071-14/+14
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-072-36/+36
* memory_bram hotfix for memories with width 1Clifford Wolf2015-01-061-3/+3
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