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author | Clifford Wolf <clifford@clifford.at> | 2015-01-17 15:39:54 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-01-17 15:39:54 +0100 |
commit | 703123114530e6010b854b5e3a5a1c0a153fa4b6 (patch) | |
tree | cfbd59ab90b17659a080fe17bea82e416699ebc9 | |
parent | a95c229e12496194b513e3623ab44f9530f272ba (diff) | |
download | yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.tar.gz yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.tar.bz2 yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.zip |
Added MUXCY and XORCY support to synth_xilinx
-rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 | ||||
-rw-r--r-- | techlibs/xilinx/arith.v | 91 | ||||
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 | ||||
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 12 |
4 files changed, 106 insertions, 2 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index b653660fa..646bd4c34 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -5,4 +5,5 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith.v)) diff --git a/techlibs/xilinx/arith.v b/techlibs/xilinx/arith.v new file mode 100644 index 000000000..a154f7740 --- /dev/null +++ b/techlibs/xilinx/arith.v @@ -0,0 +1,91 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$lcu" *) +module _80_xilinx_lcu (P, G, CI, CO); + parameter WIDTH = 2; + + input [WIDTH-1:0] P, G; + input CI; + + output [WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = WIDTH <= 2; + + wire [WIDTH-1:0] C = {CO, CI}; + wire [WIDTH-1:0] S = P & ~G; + + genvar i; + generate for (i = 0; i < WIDTH; i = i + 1) begin:slice + MUXCY muxcy ( + .CI(C[i]), + .DI(G[i]), + .S(S[i]), + .O(CO[i]) + ); + end endgenerate +endmodule + +(* techmap_celltype = "$alu" *) +module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + + wire [Y_WIDTH-1:0] P = AA ^ BB; + wire [Y_WIDTH-1:0] G = AA & BB; + wire [Y_WIDTH-1:0] C = {CO, CI}; + wire [Y_WIDTH-1:0] S = P & ~G; + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + MUXCY muxcy ( + .CI(C[i]), + .DI(G[i]), + .S(S[i]), + .O(CO[i]) + ); + XORCY xorcy ( + .CI(C[i]), + .LI(S[i]), + .O(Y[i]) + ); + end endgenerate + + assign X = P; +endmodule + diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cb290db80..138a6470f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1,4 +1,8 @@ +// See Xilinx UG953 and UG474 for a description of the cell types below. +// http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf +// http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf + module VCC(output P); assign P = 1; endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 289de4399..35bc4302e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -73,7 +73,11 @@ struct SynthXilinxPass : public Pass { log(" techmap -map +/xilinx/brams.v\n"); log("\n"); log(" fine:\n"); - log(" synth -run fine\n"); + log(" opt -fast -full\n"); + log(" memory_map\n"); + log(" opt -full\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith.v\n"); + log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); log(" abc -lut 6:8\n"); @@ -144,7 +148,11 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "synth -run fine"); + Pass::call(design, "opt -fast -full"); + Pass::call(design, "memory_map"); + Pass::call(design, "opt -full"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith.v"); + Pass::call(design, "opt -fast"); } if (check_label(active, run_from, run_to, "map_luts")) |