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Age
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Fix error handling for nested always/initial
Clifford Wolf
2017-12-02
2
-0
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+5
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Merge pull request #462 from daveshah1/up5k
Clifford Wolf
2017-11-28
1
-0
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+263
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Add remaining UltraPlus cells to ice40 techlib
David Shah
2017-11-28
1
-0
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+263
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Fixed "yosys-smtbmc -g" handling of no solution
Clifford Wolf
2017-11-27
1
-1
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+1
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Merge pull request #460 from mithro/g3-fixes
Clifford Wolf
2017-11-26
9
-8
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+45
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minisat: Make update script executable.
Tim 'mithro' Ansell
2017-11-25
1
-0
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+0
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minisat: Only define __STDC_XXX_MACROS if not already defined.
Tim 'mithro' Ansell
2017-11-25
6
-3
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+23
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minisat: Remove template with gzFile specialization.
Tim 'mithro' Ansell
2017-11-25
2
-4
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+21
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subcircuit: Class with virtual methods should have virtual destructor.
Tim 'mithro' Ansell
2017-11-25
1
-1
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+1
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Merge pull request #461 from mithro/travis-rework
Clifford Wolf
2017-11-26
1
-1
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+9
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travis: Print branches before fetching, try both locations.
Tim 'mithro' Ansell
2017-11-25
1
-1
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+9
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Merge pull request #446 from mithro/travis-rework
Clifford Wolf
2017-11-24
5
-33
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+309
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travis: Use the cache.
Tim 'mithro' Ansell
2017-11-24
1
-1
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+1
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travis: Adding gcc-4.8 and gcc-6 on Linux.
Tim 'mithro' Ansell
2017-11-24
1
-0
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+47
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travis: Reworking travis setup.
Tim 'mithro' Ansell
2017-11-24
5
-33
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+262
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2017-11-23
1
-0
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+103
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Merge pull request #455 from daveshah1/up5k
Clifford Wolf
2017-11-18
1
-0
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+103
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Remove unnecessary keep attributes
David Shah
2017-11-18
1
-5
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+5
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Merge branch 'master' into up5k
David Shah
2017-11-17
2
-5
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+29
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Add some UltraPlus cells to ice40 techlib
David Shah
2017-11-16
1
-0
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+103
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Add Verilog "automatic" keyword (ignored in synthesis)
Clifford Wolf
2017-11-23
2
-13
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+18
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Accept real-valued delay values
Clifford Wolf
2017-11-18
1
-0
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+1
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Merge pull request #452 from cr1901/master
Clifford Wolf
2017-11-18
1
-4
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+20
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Accommodate Windows-style paths during include-file processing.
William D. Jones
2017-11-14
1
-4
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+20
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Merge pull request #453 from dh73/master
Clifford Wolf
2017-11-18
14
-9
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+316
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Fixed the -vout flag to -vqm in examples/intel directory
dh73
2017-11-14
4
-4
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+4
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Initial Cyclone 10 support
dh73
2017-11-08
5
-1
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+308
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Merge https://github.com/cliffordwolf/yosys
dh73
2017-11-08
25
-449
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+588
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Organizing Speedster file names
dh73
2017-11-08
5
-4
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+4
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Add "synth_ice40 -vpr"
Clifford Wolf
2017-11-16
2
-5
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+29
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Add support for editline as replacement for readline
Clifford Wolf
2017-11-08
4
-10
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+39
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Add "ltp" command
Clifford Wolf
2017-10-31
2
-0
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+186
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Fix SMT2 handling of initstate in sub-modules
Clifford Wolf
2017-10-29
1
-0
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+3
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Fix memory corruption bug in opt_rmdff
Clifford Wolf
2017-10-26
1
-0
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+3
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Fix typo in opt_clean log message
Clifford Wolf
2017-10-26
1
-1
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+1
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Improve smtio performance by using reader thread, not writer thread
Clifford Wolf
2017-10-26
1
-10
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+30
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Use separate writer thread for talking to SMT solver to avoid read/write dead...
Clifford Wolf
2017-10-25
1
-8
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+23
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Improve p_* functions in smtio.py
Clifford Wolf
2017-10-25
1
-21
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+19
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Disable OSX in .travis.yml
Clifford Wolf
2017-10-25
1
-2
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+2
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Add ENABLE_DEBUG config flag
Clifford Wolf
2017-10-25
1
-1
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+10
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Update ABC to hg rev f6838749f234
Clifford Wolf
2017-10-25
1
-1
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+1
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Remove vhdl2verilog
Clifford Wolf
2017-10-25
2
-184
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+0
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Capsulate smt-solver read/write in separate functions
Clifford Wolf
2017-10-25
1
-8
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+24
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Fix a bug in yosys-smtbmc in ROM handling
Clifford Wolf
2017-10-25
1
-0
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+3
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Remove PSL example from tests/sva/
Clifford Wolf
2017-10-20
2
-35
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+1
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Remove all PSL support code from verific.cc
Clifford Wolf
2017-10-20
1
-179
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+17
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Merge pull request #437 from mithro/master
Clifford Wolf
2017-10-20
2
-1
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+14
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Adding COPYING file with license information.
Tim 'mithro' Ansell
2017-10-19
2
-1
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+14
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Revert 90be0d8 as it causes endless loops for some designs
Clifford Wolf
2017-10-14
1
-1
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+0
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Add "verific -vlog-libdir"
Clifford Wolf
2017-10-13
1
-0
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+12
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