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* Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-081-1/+1
* Add inout ports to cells_xtra.vClifford Wolf2018-10-082-2/+14
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-081-0/+1
* Fix for issue 594.Tom Verbeure2018-10-081-1/+2
* Add read_verilog $changed supportDan Gisselquist2018-10-081-1/+4
* ecp5: Don't map ROMs to DRAMDavid Shah2018-10-081-0/+1
* Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-10-081-1/+1
* Update to v2 YosysVS templateClifford Wolf2018-10-081-4/+4
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-10-083-6/+49
* Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-10-081-3/+9
* Update CHANGELOGClifford Wolf2018-10-081-2/+35
* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-10-081-11/+11
* Update CHANGLELOGClifford Wolf2018-10-081-5/+27
* Update ChangelogClifford Wolf2018-10-081-1/+54
* Fix Cygwin build and document needed packagesMiodrag Milanovic2018-10-083-1/+14
* Fixed typo in "verilog_write" help messageacw12512018-10-082-5/+5
* Merge remote-tracking branch 'upstream/master'Jim Lawson2018-09-1711-14/+78
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| * Merge pull request #625 from aman-goel/masterClifford Wolf2018-09-141-1/+7
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| | * Minor revision to -expose in setundef passAman Goel2018-09-101-1/+7
| * | Merge pull request #627 from acw1251/masterClifford Wolf2018-09-141-1/+1
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| | * | Fixed minor typo in "sim" help messageacw12512018-09-121-1/+1
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| * | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
| * | Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
| * | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| * | Add "make ystests"Clifford Wolf2018-08-303-0/+10
| * | Add GCC to osx deps (#620)Miodrag Milanović2018-08-281-1/+1
* | | Merge pull request #4 from YosysHQ/masterJim Lawson2018-08-283-23/+112
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| * | Merge pull request #619 from mmicko/masterClifford Wolf2018-08-282-6/+0
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| | * | Remove mercurial, since it is not needed anymoreMiodrag Milanovic2018-08-282-6/+0
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| * | Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixesClifford Wolf2018-08-281-17/+112
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| | * \ Merge branch 'master' into firrtl+modules+shiftfixesJim Lawson2018-08-2712-39/+92
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* | | | Merge pull request #3 from YosysHQ/masterJim Lawson2018-08-2712-39/+92
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| * | | Add "make coverage"Clifford Wolf2018-08-278-13/+21
| * | | Add ENABLE_GCOV build optionClifford Wolf2018-08-271-0/+11
| * | | Merge pull request #617 from mmicko/masterClifford Wolf2018-08-251-1/+1
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| | * | | static link flag on main executableMiodrag Milanovic2018-08-251-1/+1
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| * | | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
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| | * | | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | * | | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
| | * | | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| * | | | Merge pull request #614 from udif/pr_disable_dump_ptrClifford Wolf2018-08-233-9/+20
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| | * | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-233-9/+20
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| | | * | Remove unused functions.Jim Lawson2018-08-271-10/+0
| | | * | Add support for module instances.Jim Lawson2018-08-231-17/+122
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* | | | Merge pull request #1 from YosysHQ/masterJim Lawson2018-08-22196-770/+2533
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| * | | Add "verific -work" help messageClifford Wolf2018-08-221-0/+7
| * | | Add Verific -work parameterClifford Wolf2018-08-221-8/+18
| * | | Merge pull request #606 from cr1901/show-winClifford Wolf2018-08-191-3/+20
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| | * | | Update show pass documentation with Windows caveats.William D. Jones2018-08-151-1/+2
| | * | | Fix run_command() when using -format and -viewer in show pass.William D. Jones2018-08-151-2/+18
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