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| * | | | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-282-4/+15
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| | * | | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-282-4/+15
* | | | | | TypoEddie Hung2019-06-031-1/+1
* | | | | | IS_C_INVERTEDEddie Hung2019-06-031-4/+4
* | | | | | Fix `ifndefEddie Hung2019-06-031-1/+1
* | | | | | Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)Eddie Hung2019-06-034-8/+8
* | | | | | Assert that box_unique_id is indeed uniqueEddie Hung2019-06-031-2/+3
* | | | | | Remove dupeEddie Hung2019-06-031-7/+7
* | | | | | Skip internal modules when generating box_unique_idEddie Hung2019-06-031-0/+1
* | | | | | When creating new holes cell, inherit parameters tooEddie Hung2019-06-031-1/+3
* | | | | | OoopsieEddie Hung2019-06-031-1/+1
* | | | | | Consistent with xilinxEddie Hung2019-06-033-4/+4
* | | | | | Add flops as blackboxesEddie Hung2019-05-312-0/+27
* | | | | | Add FD*E_1 -> FD*E techmap rulesEddie Hung2019-05-311-5/+31
* | | | | | Techmap flops before ABC againEddie Hung2019-05-311-4/+4
* | | | | | parse_xaiger to cope with flopsEddie Hung2019-05-312-83/+123
* | | | | | ABC9 to understand flopsEddie Hung2019-05-311-46/+27
* | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-315-15/+99
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| * | | | | | Fix abc9 with (* keep *) wiresEddie Hung2019-04-232-6/+52
| * | | | | | Move clean from aigerparse to abc9Eddie Hung2019-04-232-2/+1
| * | | | | | Use nonblockingEddie Hung2019-04-231-1/+1
| * | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-228-41/+382
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-228-41/+382
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| * | | | | | | | Tidy upEddie Hung2019-04-222-7/+1
| * | | | | | | | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-222-7/+95
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* | | | | | | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
* | | | | | | | Fix issue where keep signal became PI, but also box was adding CI driverEddie Hung2019-05-301-5/+19
* | | | | | | | read_xaiger() to name box signalsEddie Hung2019-05-301-4/+8
* | | | | | | | Fix spellingEddie Hung2019-05-301-1/+1
* | | | | | | | Remove whitebox attribute from DRAMs for nowEddie Hung2019-05-301-2/+2
* | | | | | | | Do not re-sort box_module portsEddie Hung2019-05-301-4/+6
* | | | | | | | Remove whitespaceEddie Hung2019-05-301-1/+0
* | | | | | | | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
* | | | | | | | Do not double count LUT1sEddie Hung2019-05-301-1/+0
* | | | | | | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-304-12/+91
* | | | | | | | Re-enable &dc2Eddie Hung2019-05-301-1/+1
* | | | | | | | Reduce -W to 160Eddie Hung2019-05-291-1/+1
* | | | | | | | Some more realistic delays...Eddie Hung2019-05-291-7/+7
* | | | | | | | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
* | | | | | | | Call &if with -W 250Eddie Hung2019-05-291-1/+6
* | | | | | | | Bump ABCEddie Hung2019-05-291-1/+1
* | | | | | | | Rename to #23Eddie Hung2019-05-291-3/+3
* | | | | | | | Add abc_test024Eddie Hung2019-05-291-6/+19
* | | | | | | | Fix abc_test024Eddie Hung2019-05-291-4/+5
* | | | | | | | Add some debug to abc9Eddie Hung2019-05-291-1/+19
* | | | | | | | Add abc9_test022Eddie Hung2019-05-281-0/+22
* | | | | | | | Fix for abc9_test022Eddie Hung2019-05-281-2/+6
* | | | | | | | Small improvementEddie Hung2019-05-281-4/+2
* | | | | | | | From masterEddie Hung2019-05-281-1/+1
* | | | | | | | From masterEddie Hung2019-05-281-1/+1