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Cleanup use of hard-coded default parameters in light of #1945
Eddie Hung
2020-04-22
9
-60
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+54
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Merge pull request #1973 from YosysHQ/eddie/fix1966
Eddie Hung
2020-04-22
2
-2
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+4
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yosys-config: spelling
Eddie Hung
2020-04-22
1
-1
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+1
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tests: use `yosys-config --datdir` instead of hard-coded
Eddie Hung
2020-04-22
1
-1
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+3
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Merge pull request #1950 from YosysHQ/eddie/design_import
Eddie Hung
2020-04-22
3
-7
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+30
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design: add test
Eddie Hung
2020-04-16
2
-5
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+22
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design: -import to not count black/white-boxes as candidates for top
Eddie Hung
2020-04-16
1
-2
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+8
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Merge pull request #1976 from YosysHQ/dave/fix-sim-const
Claire Wolf
2020-04-22
2
-1
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+18
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sim: Fix handling of constant-connected cell inputs at startup
David Shah
2020-04-21
2
-1
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+18
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Merge pull request #1979 from whitequark/cxxrtl-go-faster
Claire Wolf
2020-04-22
2
-184
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+396
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cxxrtl: run edge detectors only once in eval().
whitequark
2020-04-22
1
-6
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+22
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cxxrtl: add an unsupported knob for manipulating clock trees.
whitequark
2020-04-22
1
-0
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+18
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cxxrtl: use log_id() where appropriate. NFC.
whitequark
2020-04-21
1
-4
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+4
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cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.
whitequark
2020-04-21
1
-65
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+186
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cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
whitequark
2020-04-21
1
-23
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+23
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cxxrtl: use one delta cycle for immediately converging netlists.
whitequark
2020-04-21
2
-11
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+21
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cxxrtl: add -O6, a shortcut for running `proc; flatten`.
whitequark
2020-04-21
1
-4
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+14
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cxxrtl: unbuffer module input wires.
whitequark
2020-04-21
1
-31
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+61
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cxxrtl: simplify generated edge detection logic.
whitequark
2020-04-21
1
-56
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+29
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cxxrtl: localize wires with multiple comb drivers, too.
whitequark
2020-04-21
1
-32
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+31
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cxxrtl: detect buffered comb wires, not just feedback wires.
whitequark
2020-04-21
1
-5
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+40
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bugpoint: Don't remove modules or cells while iterating over them.
Marcelina Kościelnicka
2020-04-22
1
-4
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+14
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intel_alm: Documentation improvements
Dan Ravensloft
2020-04-21
3
-14
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+127
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write_json: dump default parameter values
Marcelina Kościelnicka
2020-04-21
1
-0
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+10
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Use default parameter value in getParam
Marcelina Kościelnicka
2020-04-21
2
-4
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+13
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hierarchy: Convert positional parameters to named.
Marcelina Kościelnicka
2020-04-21
2
-3
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+50
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ilang, ast: Store parameter order and default value information.
Marcelina Kościelnicka
2020-04-21
6
-9
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+27
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idict: Make iterator go forward.
Marcelina Kościelnicka
2020-04-21
1
-5
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+19
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Merge pull request #1971 from YosysHQ/claire/edifkeep
Claire Wolf
2020-04-21
1
-14
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+108
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Improve net priorities in EDIF back-end
Claire Wolf
2020-04-21
1
-0
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+64
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Ignore conflicting keep attributes, unless asked not to. Fixes #1733
Claire Wolf
2020-04-20
1
-14
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+44
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Merge pull request #1851 from YosysHQ/claire/bitselwrite
Claire Wolf
2020-04-21
17
-15
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+1431
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Merge pull request #1975 from dh73/claire/bitselwrite
Eddie Hung
2020-04-20
13
-0
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+1224
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Remove '-ignore_unknown_cells' option from 'sat'
Eddie Hung
2020-04-20
1
-6
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+6
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Simplify test case script
Eddie Hung
2020-04-20
1
-30
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+17
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Remove ununsed files
Eddie Hung
2020-04-20
5
-83
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+0
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Modifications of tests as per Eddie's request
diego
2020-04-20
15
-78
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+1237
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Wrong fixed value
diego
2020-04-17
1
-1
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+1
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Adding tests for dynamic part select optimisation
diego
2020-04-16
7
-0
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+161
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Make mask-and-shift the default for bitselwrite
Claire Wolf
2020-04-16
1
-1
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+1
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Add LookaheadRewriter for proper bitselwrite support
Claire Wolf
2020-04-16
4
-4
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+144
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Improved rewrite code for writing to bit slice (disabled for now)
Claire Wolf
2020-04-15
1
-12
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+64
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Merge pull request #1961 from whitequark/paramod-original-name
whitequark
2020-04-21
3
-11
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+7
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ast, rpc: record original name of $paramod\* as \hdlname attribute.
whitequark
2020-04-18
3
-11
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+7
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tests: remove write_ilang
Eddie Hung
2020-04-20
2
-3
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+0
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Merge pull request #1972 from YosysHQ/eddie/bug1970
Eddie Hung
2020-04-20
2
-16
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+52
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abc9: -prep_lut to be more robust
Eddie Hung
2020-04-20
1
-16
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+33
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abc9: add testcase reduced from #1970
Eddie Hung
2020-04-20
1
-0
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+19
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Merge pull request #1964 from YosysHQ/claire/sformatf
Claire Wolf
2020-04-20
1
-8
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+38
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Extend support for format strings in Verilog front-end
Claire Wolf
2020-04-18
1
-8
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+38
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