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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 09:38:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 09:38:29 -0700 |
| commit | 34d8ff8b569262da28175b56099e099413313022 (patch) | |
| tree | 6191b595ff2ce2802eb4f9623540cfa8d7ad1a0d | |
| parent | ae115fa3aac9acf7534b3f7c08afaa1b86bfc4ad (diff) | |
| download | yosys-34d8ff8b569262da28175b56099e099413313022.tar.gz yosys-34d8ff8b569262da28175b56099e099413313022.tar.bz2 yosys-34d8ff8b569262da28175b56099e099413313022.zip | |
abc9: add testcase reduced from #1970
| -rw-r--r-- | tests/various/abc9.ys | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 0c7695089..6e2415ad7 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -53,3 +53,22 @@ assign q = w; endmodule EOT abc9 -lut 4 -dff + + +design -reset +read_verilog -icells -specify <<EOT +(* abc9_lut=1, blackbox *) +module LUT2(input [1:0] i, output o); +parameter [3:0] mask = 0; +assign o = i[0] ? (i[1] ? mask[3] : mask[2]) + : (i[1] ? mask[1] : mask[0]); +specify + (i *> o) = 1; +endspecify +endmodule + +module top(input [1:0] i, output o); +LUT2 #(.mask(4'b0)) lut (.i(i), .o(o)); +endmodule +EOT +abc9 |