iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| \| \| * \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-07-24	199	-1214/+9423
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\| \| * \| \ \ \ \ \	Merge pull request #1249 from mmicko/anlogic_fix	Clifford Wolf	2019-08-07	1	-16/+8
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\| \| \| * \| \| \| \| \| \|	anlogic : Fix alu mapping	Miodrag Milanovic	2019-08-03	1	-16/+8
\| \| * \| \| \| \| \| \| \|	Merge pull request #1252 from YosysHQ/clifford/fix1231	Clifford Wolf	2019-08-07	1	-15/+2
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\| \| \| * \| \| \| \| \| \| \|	Fix handling of functions/tasks without top-level begin-end block, fixes #1231	Clifford Wolf	2019-08-06	1	-15/+2
\| \| * \| \| \| \| \| \| \| \|	Merge pull request #1253 from YosysHQ/clifford/check	Clifford Wolf	2019-08-07	3	-9/+17
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\| \| \| * \| \| \| \| \| \| \| \|	Be less aggressive with running design->check()	Clifford Wolf	2019-08-06	3	-9/+17
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\| \| * \| \| \| \| \| \| \| \|	Merge pull request #1257 from YosysHQ/clifford/cellcosts	Clifford Wolf	2019-08-07	3	-109/+103
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\| \| \| * \| \| \| \| \| \| \|	Tweak default gate costs, cleanup "stat -tech cmos"	Clifford Wolf	2019-08-07	2	-20/+10
\| \| \| * \| \| \| \| \| \| \|	Redesign of cell cost API	Clifford Wolf	2019-08-07	2	-93/+97
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\| \| * \| \| \| \| \| \| \|	Update CHANGELOG	David Shah	2019-08-07	1	-0/+2
\| \| * \| \| \| \| \| \| \|	Merge pull request #1241 from YosysHQ/clifford/jsonfix	David Shah	2019-08-07	2	-36/+71
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\| \| \| * \| \| \| \| \| \|	Update JSON front-end to process new attr/param encoding	Clifford Wolf	2019-08-01	1	-23/+34
\| \| \| * \| \| \| \| \| \|	Implement improved JSON attr/param encoding	Clifford Wolf	2019-08-01	1	-13/+37
\| \| * \| \| \| \| \| \| \|	Merge pull request #1232 from YosysHQ/dave/write_gzip	David Shah	2019-08-06	4	-7/+79
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\| \| \| * \| \| \| \| \| \|	Add test for writing gzip-compressed files	David Shah	2019-08-06	2	-0/+18
\| \| \| * \| \| \| \| \| \|	Add support for writing gzip-compressed files	David Shah	2019-08-06	2	-7/+61
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\| \| * \| \| \| \| \| \|	Merge pull request #1251 from YosysHQ/clifford/nmux	Clifford Wolf	2019-08-06	19	-42/+174
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\| \| \| * \| \| \| \| \|	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	Clifford Wolf	2019-08-06	19	-42/+174
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\| \| * \| \| \| \| \|	Merge pull request #1242 from jfng/fix-proc_prune-partial	whitequark	2019-08-03	1	-2/+11
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\| \| \| * \| \| \| \| \|	proc_prune: Promote partially redundant assignments.	Jean-François Nguyen	2019-08-01	1	-2/+11
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\| \| * \| \| \| \| \|	Merge pull request #1238 from mmicko/vsbuild_fix	Clifford Wolf	2019-08-02	2	-1/+2
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\| \| \| * \| \| \| \| \|	Visual Studio build fix	Miodrag Milanovic	2019-07-31	2	-1/+2
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\| \| * \| \| \| \| \|	Merge pull request #1239 from mmicko/mingw_fix	Clifford Wolf	2019-08-02	11	-25/+37
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\| \| \| * \| \| \| \| \|	Fix linking issue for new mxe and pthread	Miodrag Milanovic	2019-08-01	1	-1/+2
\| \| \| * \| \| \| \| \|	Fix yosys linking for mxe	Miodrag Milanovic	2019-08-01	1	-1/+1
\| \| \| * \| \| \| \| \|	New mxe hacks needed to support 2ca237e	Miodrag Milanovic	2019-08-01	1	-0/+4
\| \| \| * \| \| \| \| \|	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-01	10	-23/+30
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\| * \| \| \| \| \| \|	Do not pack registers if (* keep *)	Eddie Hung	2019-08-07	1	-0/+20
* \| \| \| \| \| \| \|	DSP48E1 sim model: add SIMD tests	David Shah	2019-08-08	3	-3/+113
* \| \| \| \| \| \| \|	DSP48E1 model: test CE inputs	David Shah	2019-08-08	2	-7/+17
* \| \| \| \| \| \| \|	DSP48E1 sim model: fix seq tests and add preadder tests	David Shah	2019-08-08	2	-6/+91
* \| \| \| \| \| \| \|	DSP48E1 sim model: seq test working	David Shah	2019-08-08	3	-16/+60
* \| \| \| \| \| \| \|	DSP48E1 sim model: Comb, no pre-adder, mode working	David Shah	2019-08-08	2	-8/+13
* \| \| \| \| \| \| \|	[wip] sim model testing	David Shah	2019-08-08	4	-15/+77
* \| \| \| \| \| \| \|	[wip] sim model testing	David Shah	2019-08-08	3	-40/+360
* \| \| \| \| \| \| \|	[wip] DSP48E1 sim model improvements	David Shah	2019-08-07	1	-6/+82
* \| \| \| \| \| \| \|	[wip] DSP48E1 sim model improvements	David Shah	2019-08-06	1	-23/+120
* \| \| \| \| \| \| \|	[wip] DSP48E1 sim model improvements	David Shah	2019-08-06	1	-8/+75
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* \| \| \| \| \| \|	Add comment about supporting $dffe in ice40_dsp	Eddie Hung	2019-08-01	1	-0/+1
* \| \| \| \| \| \|	Pack P register properly	Eddie Hung	2019-08-01	1	-2/+4
* \| \| \| \| \| \|	Trim Y_WIDTH	Eddie Hung	2019-08-01	1	-5/+3
* \| \| \| \| \| \|	Add DSP_SIGNEDONLY back	Eddie Hung	2019-08-01	1	-0/+16
* \| \| \| \| \| \|	DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH	Eddie Hung	2019-08-01	2	-5/+12
* \| \| \| \| \| \|	Change $__softmul back to $mul	Eddie Hung	2019-08-01	1	-0/+1
* \| \| \| \| \| \|	Cope with sign extension in mul2dsp	Eddie Hung	2019-08-01	2	-14/+14
* \| \| \| \| \| \|	Revert "Do not do sign extension in techmap; let packer do it"	Eddie Hung	2019-08-01	1	-5/+14
* \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-01	25	-86/+219
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\| * \| \| \| \| \|	Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map	Eddie Hung	2019-08-01	1	-3/+3
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\| \| * \| \| \| \|	RST -> RSTBRST for RAMB8BWER	Eddie Hung	2019-07-29	1	-3/+3
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