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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-29 16:05:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-29 16:05:44 -0700 |
| commit | 66806085db7d730c27a330e541f8aecbba3bd342 (patch) | |
| tree | a2e60038639714df7b7b0aaa1791e9127c1e2c2f | |
| parent | b4f38cca77a78884ce215190935af78cae92c4db (diff) | |
| download | yosys-66806085db7d730c27a330e541f8aecbba3bd342.tar.gz yosys-66806085db7d730c27a330e541f8aecbba3bd342.tar.bz2 yosys-66806085db7d730c27a330e541f8aecbba3bd342.zip | |
RST -> RSTBRST for RAMB8BWER
| -rw-r--r-- | techlibs/xilinx/xc6s_brams_map.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v index c9b33af42..16fd15e74 100644 --- a/techlibs/xilinx/xc6s_brams_map.v +++ b/techlibs/xilinx/xc6s_brams_map.v @@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK2 ^ !CLKPOL2), .ENBRDEN(A1EN), .REGCEBREGCE(|1), - .RSTB(|0) + .RSTBRST(|0) ); endmodule @@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end else begin @@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end endgenerate |