[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>

4 files changed, 77 insertions, 15 deletions

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index a6ab98926..4e26ea5c9 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -728,7 +728,7 @@ module DSP48E1 (
                     maj_xyz_gated[23] ^ int_carry_out[1],
                     1'bx
                 };
-        end else if (USE_SIMD == "FOUR48") begin
+        end else begin
             assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin};
             assign int_carry_in[3:1] = int_carry_out[2:0];
             assign ext_carry_out = {
@@ -738,7 +738,7 @@ module DSP48E1 (
         end
 
         genvar i;
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < 4; i = i + 1)
             assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]}
                                                               + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i];
     endgenerate
diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore
index 40d61ccce..ef3699bd2 100644
--- a/techlibs/xilinx/tests/.gitignore
+++ b/techlibs/xilinx/tests/.gitignore
@@ -4,4 +4,8 @@ bram1_[0-9]*/
 bram2.log
 bram2_syn.v
 bram2_tb
-dsp_work*/
\ No newline at end of file
+dsp_work*/
+test_dsp_model_ref.v
+test_dsp_model_uut.v
+test_dsp_model
+*.vcd
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh
new file mode 100644
index 000000000..5455294da
--- /dev/null
+++ b/techlibs/xilinx/tests/test_dsp_model.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+set -ex
+sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
+fi
+for tb in mult_noreg_nopreadd_nocasc
+do
+	iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
+	vvp -N ./test_dsp_model
+done
diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v
index 2ecaabfe7..f8039aa15 100644
--- a/techlibs/xilinx/tests/test_dsp_model.v
+++ b/techlibs/xilinx/tests/test_dsp_model.v
@@ -83,12 +83,21 @@ module testbench;
 
 	reg config_valid = 0;
 	task drc;
-		config_valid = 1;
-		if (AREG != 2 && INMODE[0]) config_valid = 0;
-		if (BREG != 2 && INMODE[4]) config_valid = 0;
-		if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
-		if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0;
-		if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
+		begin
+			config_valid = 1;
+			if (AREG != 2 && INMODE[0]) config_valid = 0;
+			if (BREG != 2 && INMODE[4]) config_valid = 0;
+			if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
+			if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
+			if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
+			if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
+			if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0;
+			if (OPMODE[6:4] == 3'b111) config_valid = 0;
+			if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0;
+			if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0;
+			if (CARRYINSEL == 3'b010 && OPMODE != 7'b0001010) config_valid = 0;
+			if (CARRYINSEL == 3'b001 && OPMODE != 7'b1010101) config_valid = 0;
+		end
 	endtask
 
 	initial begin
@@ -109,7 +118,7 @@ module testbench;
 		#5;
 		CLK = 1'b1;
 		#10;
-		CLK = 1'b0
+		CLK = 1'b0;
 		#5;
 		CLK = 1'b1;
 		#10;
@@ -118,7 +127,8 @@ module testbench;
 
 		repeat (300) begin
 			clkcycle;
-			do begin
+			config_valid = 0;
+			while (!config_valid) begin
 				A = $urandom;
 				ACIN = $urandom;
 				B = $urandom;
@@ -129,10 +139,12 @@ module testbench;
 
 				{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom;
 				{ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom;
-				OPMODE = $urandom;
+				OPMODE = $urandom; 
+				if ($urandom & 1'b1)
+					OPMODE[3:0] = 4'b0101; // test multiply more than other modes
 				{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
 				drc;
-			end while (!config_valid);
+			end
 		end
 
 		if (errcount == 0) begin
@@ -194,6 +206,7 @@ module testbench;
 		.BCIN          (BCIN),
 		.C             (C),
 		.CARRYCASCIN   (CARRYCASCIN),
+		.CARRYINSEL    (CARRYINSEL),
 		.CEA1          (CEA1),
 		.CEA2          (CEA2),
 		.CEAD          (CEAD),
@@ -275,6 +288,7 @@ module testbench;
 		.BCIN          (BCIN),
 		.C             (C),
 		.CARRYCASCIN   (CARRYCASCIN),
+		.CARRYINSEL    (CARRYINSEL),
 		.CEA1          (CEA1),
 		.CEA2          (CEA2),
 		.CEAD          (CEAD),
@@ -305,6 +319,39 @@ module testbench;
 		.RSTM          (RSTM),
 		.RSTP          (RSTP)
 	);
-
-
 endmodule
+
+module mult_noreg_nopreadd_nocasc;
+	testbench #(
+		.ACASCREG           (0),
+		.ADREG              (0),
+		.ALUMODEREG         (0),
+		.AREG               (0),
+		.AUTORESET_PATDET   ("NO_RESET"),
+		.A_INPUT            ("DIRECT"),
+		.BCASCREG           (0),
+		.BREG               (0),
+		.B_INPUT            ("DIRECT"),
+		.CARRYINREG         (0),
+		.CARRYINSELREG      (0),
+		.CREG               (0),
+		.DREG               (0),
+		.INMODEREG          (0),
+		.MREG               (0),
+		.OPMODEREG          (0),
+		.PREG               (0),
+		.SEL_MASK           ("MASK"),
+		.SEL_PATTERN        ("PATTERN"),
+		.USE_DPORT          ("FALSE"),
+		.USE_MULT           ("DYNAMIC"),
+		.USE_PATTERN_DETECT ("NO_PATDET"),
+		.USE_SIMD           ("ONE48"),
+		.MASK               (48'h3FFFFFFFFFFF),
+		.PATTERN            (48'h000000000000),
+		.IS_ALUMODE_INVERTED(4'b0),
+		.IS_CARRYIN_INVERTED(1'b0),
+		.IS_CLK_INVERTED    (1'b0),
+		.IS_INMODE_INVERTED (5'b0),
+		.IS_OPMODE_INVERTED (7'b0)
+	) testbench ();
+endmodule
\ No newline at end of file